公开(公告)号：US20200185349A1

公开(公告)日：2020-06-11

申请号：US16788428

申请日：2020-02-12

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/48 ,  H01L23/373 ,  H01L23/367 ,  H05K3/46 ,  H05K3/30 ,  H01L23/538 ,  H01L23/34

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US10453786B2

公开(公告)日：2019-10-22

申请号：US15000257

申请日：2016-01-19

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Nancy Cecelia Stoffel ,  Risto Ilkka Tuominen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/055 ,  H01L23/498 ,  H01L21/48 ,  H01L25/16 ,  H01L23/04 ,  H01L23/08 ,  H01L23/15 ,  H01L23/538 ,  H01L25/10

Abstract: An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.

公开(公告)号：US20190311981A1

公开(公告)日：2019-10-10

申请号：US16448691

申请日：2019-06-21

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Nancy Cecelia Stoffel ,  Risto Ilkka Tuominen

IPC: H01L23/498 ,  H01L23/08 ,  H01L23/15 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31 ,  H01L23/055 ,  H01L23/04

Abstract: An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.

公开(公告)号：US20180033762A1

公开(公告)日：2018-02-01

申请号：US15729889

申请日：2017-10-11

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/00 ,  H01L23/373 ,  H01L25/10 ,  H05K3/46 ,  H01L23/48 ,  H05K3/30 ,  H01L23/367 ,  H01L23/34 ,  H01L23/538 ,  H05K3/36 ,  H01L23/433 ,  H01L23/42 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L24/32 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/2711 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/46 ,  H01L2224/80365 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/207 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/183 ,  H05K1/185 ,  H05K3/301 ,  H05K3/305 ,  H05K3/306 ,  H05K3/366 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/302 ,  Y02P70/613

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US20170263539A1

公开(公告)日：2017-09-14

申请号：US15601735

申请日：2017-05-22

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

公开(公告)号：US09613843B2

公开(公告)日：2017-04-04

申请号：US14512562

申请日：2014-10-13

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/78 ,  H01L25/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/525 ,  H01L23/528

CPC classification number: H01L24/46 ,  H01L21/6835 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3164 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03466 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/24137 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/4847 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/8203 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1302 ,  H01L2924/13023 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

公开(公告)号：US20170077014A1

公开(公告)日：2017-03-16

申请号：US15363237

申请日：2016-11-29

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract translation: 半导体器件模块包括电介质层，具有耦合到电介质层的第一表面的半导体器件和具有耦合到电介质层的第一表面的导电垫片。 半导体器件还包括具有耦合到半导体器件的第二表面的第一表面和导电垫片的第二表面的导电散热器。 金属化层耦合到半导体器件的第一表面和导电垫片的第一表面。 金属化层延伸穿过电介质层，并通过导电垫片和散热器与半导体器件的第二表面电连接。

公开(公告)号：US20160183376A1

公开(公告)日：2016-06-23

申请号：US14580269

申请日：2014-12-23

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Risto Ilkka Tuominen

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/00 ,  H05K1/09 ,  H05K1/11

CPC classification number: H01L23/49827 ,  H01L22/12 ,  H01L22/14 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/19105 ,  H01L2924/37001

Abstract: An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.

Abstract translation: 提供电子包装。 电子封装包括基板和由相应的多个预定义的通孔图案限定的多个通孔。 电子封装还包括设置在基板的部分上的金属组合层，以提供多个预定义的通孔位置和多个通孔中的多个预定义的通孔图案。 此外，电子封装包括设置在金属叠层的至少一部分上的第一导电层。 此外，电子封装包括设置在第一导电层上的第二导电层，其中多个通孔至少部分地设置在金属组合层，第一导电层和第二导电层中。

公开(公告)号：US09209151B2

公开(公告)日：2015-12-08

申请号：US14037728

申请日：2013-09-26

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/538 ,  H05K1/18 ,  H01L23/34 ,  H05K3/46 ,  H05K1/02 ,  H05K3/30

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract translation: 封装结构包括介电层，至少一个连接到电介质层的半导体器件，一个或多个施加到电介质层的电介质片和半导体器件，以将半导体器件嵌入其中，并且多个 形成在形成在电介质层和一个或多个电介质层中的至少一个中的半导体器件上的通孔。 封装结构还包括形成在通孔中的金属互连和在封装结构的一个或多个向外表面上以形成与半导体器件的电互连的金属互连。 电介质层由在层压过程中不流动的材料组成，并且所述一个或多个电介质片中的每一个由可固化材料构成，所述可固化材料构造成在层压过程中固化时熔化和流动，以便填充任何空气 半导体器件周围的间隙。

公开(公告)号：US20140138807A1

公开(公告)日：2014-05-22

申请号：US14165725

申请日：2014-01-28

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.