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公开(公告)号:US08754508B2
公开(公告)日:2014-06-17
申请号:US13598196
申请日:2012-08-29
申请人: Hsien-Wei Chen , Hung-Jui Kuo
发明人: Hsien-Wei Chen , Hung-Jui Kuo
IPC分类号: H01L29/06
CPC分类号: H01L23/3192 , H01L23/3114 , H01L23/525 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L24/11 , H01L24/13 , H01L2224/11334 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/13101 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13181 , H01L2924/014 , H01L2924/00014
摘要: A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration.
摘要翻译: 半导体器件包括位于两个相邻金属线之间的聚合物层中的凹槽,以及在再分布金属线上的钝化层或抗电迁移层上,以增加对电迁移的抵抗力。
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公开(公告)号:US20140061923A1
公开(公告)日:2014-03-06
申请号:US13598196
申请日:2012-08-29
申请人: Hsien-Wei Chen , Hung-Jui Kuo
发明人: Hsien-Wei Chen , Hung-Jui Kuo
IPC分类号: H01L23/485 , H01L21/768
CPC分类号: H01L23/3192 , H01L23/3114 , H01L23/525 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L24/11 , H01L24/13 , H01L2224/11334 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/13101 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13181 , H01L2924/014 , H01L2924/00014
摘要: A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration.
摘要翻译: 半导体器件包括位于两个相邻金属线之间的聚合物层中的凹槽,以及在再分布金属线上的钝化层或抗电迁移层上,以增加对电迁移的抵抗力。
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公开(公告)号:US20140015122A1
公开(公告)日:2014-01-16
申请号:US13546300
申请日:2012-07-11
申请人: Meng-Wei Chou , Hung-Jui Kuo , Ming-Che Ho , Chung-Shi Liu
发明人: Meng-Wei Chou , Hung-Jui Kuo , Ming-Che Ho , Chung-Shi Liu
IPC分类号: H01L21/768 , H01L23/498
CPC分类号: H01L23/525 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02331 , H01L2224/03464 , H01L2224/0361 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05184 , H01L2224/05548 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2924/00014 , H01L2924/12042 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要: A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure.
摘要翻译: 形成后钝化互连的方法包括在衬底上形成钝化层,其中金属焊盘嵌入钝化层中,在钝化层上沉积第一介电层,将第一图案化工艺应用于第一介电层以形成 第一开口,在第一开口上形成第一种子层,用导电材料填充第一开口,在第一介电层上沉积第二介电层,向第二介电层施加第二图案化工艺以形成第二开口,形成 在第二开口上方的凸块下金属化结构,并且在凸块下金属化结构之上安装互连凸块。
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公开(公告)号:US20130026644A1
公开(公告)日:2013-01-31
申请号:US13192113
申请日:2011-07-27
申请人: Chen-Hua Yu , Chung-Shi Liu , Hung-Jui Kuo
发明人: Chen-Hua Yu , Chung-Shi Liu , Hung-Jui Kuo
IPC分类号: H01L23/528 , H01L21/28 , H01L23/31
CPC分类号: H01L23/5226 , G03F7/0045 , G03F7/095 , H01L21/311 , H01L21/76804 , H01L24/24 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/24146 , H01L2224/73259 , H01L2224/8203 , H01L2224/82101 , H01L2224/82106 , H01L2224/94 , H01L2225/06524 , H01L2924/10253 , H01L2924/1431 , H01L2924/1434 , H01L2224/82 , H01L2224/81
摘要: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.
摘要翻译: 提供了一种用于在半导体衬底上形成光致抗蚀剂的系统和方法。 一个实施方案包括具有浓度梯度的光致抗蚀剂。 浓度梯度可以通过使用一系列干膜光致抗蚀剂形成,其中每个单独的干膜光致抗蚀剂具有不同的浓度。 单独的干膜光致抗蚀剂可以单独形成,然后在图案化之前放置在半导体衬底上。 一旦被图案化,通过光致抗蚀剂的开口可以具有锥形侧壁,允许更好地覆盖种子层,以及更均匀的工艺以通过光致抗蚀剂形成导电材料。
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公开(公告)号:US20120064712A1
公开(公告)日:2012-03-15
申请号:US12881495
申请日:2010-09-14
申请人: Yi-Yang Lei , Hung-Jui Kuo , Chung-Shi Liu
发明人: Yi-Yang Lei , Hung-Jui Kuo , Chung-Shi Liu
IPC分类号: H01L21/768
CPC分类号: H01L21/67028 , H01L23/3114 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03831 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11622 , H01L2224/1308 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要: A method of forming a device includes providing a wafer including a substrate; and forming an under-bump metallurgy (UBM) layer including a barrier layer overlying the substrate and a seed layer overlying the barrier layer. A metal bump is formed directly over a first portion of the UBM layer, wherein a second portion of the UBM layer is not covered by the metal bump. The second portion of the UBM layer includes a seed layer portion and a barrier layer portion. A first etch is performed to remove the seed layer portion, followed by a first rinse step performed on the wafer. A second etch is performed to remove the barrier layer portion, followed by a second rinse step performed on the wafer. At least a first switch time from the first etch to the first rinse step and a second switch time from the second etch to the second rinse step is less than about 1 second.
摘要翻译: 一种形成器件的方法包括提供包括衬底的晶片; 以及形成包括覆盖在衬底上的阻挡层和覆盖在阻挡层上的种子层的凸起下金属(UBM)层。 直接在UBM层的第一部分上形成金属凸块,其中UBM层的第二部分不被金属凸块覆盖。 UBM层的第二部分包括种子层部分和阻挡层部分。 进行第一蚀刻以除去种子层部分,接着在晶片上执行第一漂洗步骤。 执行第二蚀刻以去除阻挡层部分,接着在晶片上执行第二冲洗步骤。 从第一蚀刻到第一漂洗步骤的至少第一切换时间和从第二蚀刻到第二冲洗步骤的第二切换时间小于约1秒。
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公开(公告)号:US20120009777A1
公开(公告)日:2012-01-12
申请号:US12832005
申请日:2010-07-07
申请人: Chung-Shi Liu , Hung-Jui Kuo , Meng-Wei Chou
发明人: Chung-Shi Liu , Hung-Jui Kuo , Meng-Wei Chou
IPC分类号: H01L21/768
CPC分类号: H01L24/03 , H01L23/3157 , H01L24/05 , H01L24/11 , H01L2224/02311 , H01L2224/02331 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/03831 , H01L2224/0401 , H01L2224/05001 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/11424 , H01L2224/11462 , H01L2224/11464 , H01L2224/11622 , H01L2224/1308 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要: A method of forming a device includes forming an under-bump metallurgy (UBM) layer including a barrier layer and a seed layer over the barrier layer; and forming a mask over the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. The first portion of the UBM layer includes a barrier layer portion and a seed layer portion. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A wet etch is performed to remove the seed layer portion. A dry etch is performed to remove the barrier layer portion.
摘要翻译: 一种形成器件的方法包括在阻挡层上形成包括阻挡层和籽晶层的凸起下金属(UBM)层; 并在UBM层上形成掩模。 掩模覆盖UBM层的第一部分,并且UBM层的第二部分通过掩模中的开口暴露。 UBM层的第一部分包括阻挡层部分和种子层部分。 在UBM层的开口和第二部分上形成金属凸块。 然后取下面具。 执行湿蚀刻以去除种子层部分。 执行干蚀刻以去除阻挡层部分。
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公开(公告)号:US08748306B2
公开(公告)日:2014-06-10
申请号:US13198767
申请日:2011-08-05
申请人: Yi-Yang Lei , Hung-Jui Kuo , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人: Yi-Yang Lei , Hung-Jui Kuo , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
CPC分类号: H01L24/11 , H01L23/3171 , H01L23/3192 , H01L24/02 , H01L24/05 , H01L24/13 , H01L2224/0239 , H01L2224/0401 , H01L2224/05024 , H01L2224/05569 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/11334 , H01L2224/11849 , H01L2224/119 , H01L2224/1191 , H01L2224/131 , H01L2224/13111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/181 , H01L2924/01029 , H01L2924/01013 , H01L2924/01028 , H01L2924/014 , H01L2924/01047 , H01L2224/1181 , H01L2924/04953 , H01L2924/04941 , H01L2924/00 , H01L2224/05552
摘要: A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured.
摘要翻译: 在晶片衬底上形成晶片级芯片级封装焊料凸块的方法包括使用激光清洗焊料凸块的表面,以在焊料凸点回流之后从焊料凸块的表面去除残留的模塑料,并且液态模塑 化合物被施用和固化。
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公开(公告)号:US20140008785A1
公开(公告)日:2014-01-09
申请号:US13542528
申请日:2012-07-05
申请人: Tsung-Shu Lin , Hung-Jui Kuo , Yi-Wen Wu
发明人: Tsung-Shu Lin , Hung-Jui Kuo , Yi-Wen Wu
IPC分类号: H01L23/52 , H01L21/50 , H01L23/488
CPC分类号: H01L24/73 , H01L23/3121 , H01L23/5389 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/107 , H01L2924/0002 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要: A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate.
摘要翻译: 封装封装(PoP)器件包括在衬底上的底部封装和耦合底部封装和衬底的第一组导电元件。 PoP器件还包括在底部封装上的顶部封装以及将顶部封装耦合到衬底的再分配层。 形成PoP器件的方法包括将第一封装耦合到衬底; 以及在所述第一封装和所述衬底的顶表面上形成再分布层。 该方法还包括将第二包装物耦合到再分配层,其中再分配层将第二包装物耦合到基底。
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公开(公告)号:US08446007B2
公开(公告)日:2013-05-21
申请号:US12784327
申请日:2010-05-20
申请人: Hung-Jui Kuo , Chung-Shi Liu , Chen-Hua Yu
发明人: Hung-Jui Kuo , Chung-Shi Liu , Chen-Hua Yu
IPC分类号: H01L23/52
CPC分类号: H01L22/12 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05552 , H01L2224/05555 , H01L2224/06131 , H01L2224/13099 , H01L2224/131 , H01L2224/14104 , H01L2224/81193 , H01L2224/81801 , H01L2924/0001 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K1/111 , H05K3/3436 , H05K2201/09427 , Y02P70/611 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要: An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.
摘要翻译: 集成电路结构包括从由半导体芯片和封装基板构成的组中选择的工件。 工件包括分布在工件的主表面上的多个凸块下金属(UBM); 以及多个金属凸块,其中所述多个金属凸块中的每一个直接在所述多个UBM中的一个上,并且电连接到所述多个UBM中的一个。 多个UBM和多个金属凸块被分配有覆盖偏移,多个UBM中的至少一些与多个金属凸块中相应的上覆的UBM不对准。
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公开(公告)号:US20120319270A1
公开(公告)日:2012-12-20
申请号:US13162394
申请日:2011-06-16
申请人: Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
发明人: Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
IPC分类号: H01L23/48
CPC分类号: H01L23/562 , H01L23/293 , H01L23/3114 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05569 , H01L2224/05572 , H01L2224/131 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
摘要: A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.
摘要翻译: 一种结构包括半导体衬底上的金属焊盘,具有金属焊盘上方的一部分的钝化层以及钝化层上的第一聚酰亚胺层,其中第一聚酰亚胺层具有第一厚度和第一杨氏模量。 后钝化互连(PPI)包括在第一聚酰亚胺层之上的第一部分,以及延伸到钝化层和第一聚酰亚胺层中的第二部分。 PPI电耦合到金属垫。 第二个聚酰亚胺层位于PPI之上。 第二聚酰亚胺层具有第二厚度和第二杨氏模量。 厚度比和杨氏模量比中的至少一个大于1.0,其中厚度比是第一厚度与第二厚度的比率,杨氏模量比是第二杨氏模量与第一杨氏模量之比 模数。
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