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    BGA BALLOUT PARTITION TECHNIQUES FOR SIMPLIFIED LAYOUT IN MOTHERBOARD WITH MULTIPLE POWER SUPPLY RAIL
    2.
    发明申请
    BGA BALLOUT PARTITION TECHNIQUES FOR SIMPLIFIED LAYOUT IN MOTHERBOARD WITH MULTIPLE POWER SUPPLY RAIL 有权
    BGA BALLOUT分段技术，用于多台电源轨道车载板上的简化布局

    公开(公告)号：US20160093563A1

    公开(公告)日：2016-03-31

    申请号：US14497825

    申请日：2014-09-26

    Applicant: INVENSAS CORPORATION

    Inventor： Yong Chen ,  Zhuowen Sun ,  Kyong-Mo Bang

    IPC: H01L23/498 ,  H05K1/02

    CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/181 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

    Abstract translation: 微电子封装可以包括衬底和微电子元件。 衬底可以包括在衬底的表面处的区域阵列中至少包括第一电源端子和其他端子的端子。 基板还可以包括电耦合到第一电源端子的功率平面元件。 区域阵列可以具有周边边缘和在平行于表面的方向上从周边边缘向内延伸的端子之间的连续间隙。 间隙的相对侧上的端子可以彼此间隔开至少1.5倍的端子的最小间距。 功率平面元件可以在间隙内从至少外围边缘至少延伸到第一电源端子。 每个第一电源端子可以通过两个或更多其它端子与外围边缘分离。

    COMPACT MICROELECTRONIC ASSEMBLY HAVING REDUCED SPACING BETWEEN CONTROLLER AND MEMORY PACKAGES
    3.
    发明申请
    COMPACT MICROELECTRONIC ASSEMBLY HAVING REDUCED SPACING BETWEEN CONTROLLER AND MEMORY PACKAGES 有权
    具有控制器和存储器封装之间的减少间隔的紧凑型微电子组件

    公开(公告)号：US20160093340A1

    公开(公告)日：2016-03-31

    申请号：US14496159

    申请日：2014-09-25

    Applicant: Invensas Corporation

    Inventor： Zhuowen Sun ,  Yong Chen

    IPC: G11C5/06 ,  G11C5/02

    CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L24/00

    Abstract: A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.

    Abstract translation: 微电子封装在具有第一和第二半区域的衬底的表面上具有端子，每个半区域从对角线延伸，该对角线将第一表面和第一表面的相应的相对角分成两部分。 用于承载前半部分中的数据和地址信息的终端提供对第一存储器存储阵列的第一存储器通道访问，并且用于承载第二半部分中的数据和地址信息的终端提供对第二存储器存储阵列的第二存储器通道访问。 封装可以包括覆盖在基板的相同表面上的第一和第二微电子元件，其可以以横向取向堆叠。

    In-package fly-by signaling
    7.
    发明授权
    In-package fly-by signaling 有权
    包装内飞行信号

    公开(公告)号：US09241420B2

    公开(公告)日：2016-01-19

    申请号：US14275098

    申请日：2014-05-12

    Applicant: Invensas Corporation

    Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Yong Chen

    IPC: H01L23/48 ,  H01L23/34 ,  H01L21/70 ,  H05K7/14 ,  H01L23/13 ,  H01L25/065 ,  G11C5/06 ,  H01L23/498 ,  H01L23/31

    CPC classification number: H05K7/1459 ,  G11C5/063 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0655 ,  H01L2224/4824 ,  H01L2924/15311

    Abstract: In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.

    Abstract translation: 可以在具有在封装衬底上的地址线的多芯片微电子封装中提供封装内的飞越信号，该封装衬底被配置为将地址信息传送到具有来自封装端子的第一延迟的衬底上的第一连接区域，并且地址 线路被配置为将地址信息超出第一连接区域至少至少具有来自大于第一延迟的端子的具有第二延迟的第二连接区域。 第一微电子元件（例如，半导体芯片）的地址输入可以与第一连接区域处的每个地址线耦合，并且第二微电子元件的地址输入可以在第二连接区域与每个地址线耦合 。

    IN-PACKAGE FLY-BY SIGNALING
    8.
    发明申请
    IN-PACKAGE FLY-BY SIGNALING 有权
    IN-PACKAGE FLY-BY信号

    公开(公告)号：US20140268537A1

    公开(公告)日：2014-09-18

    申请号：US14275098

    申请日：2014-05-12

    Applicant: INVENSAS CORPORATION

    Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Yong Chen

    IPC: H05K7/14

    CPC classification number: H05K7/1459 ,  G11C5/063 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0655 ,  H01L2224/4824 ,  H01L2924/15311

    Abstract: In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.

    Abstract translation: 可以在具有在封装衬底上的地址线的多芯片微电子封装中提供封装内的飞越信号，该封装衬底被配置为将地址信息传送到具有来自封装端子的第一延迟的衬底上的第一连接区域，并且地址 线路被配置为将地址信息超出第一连接区域至少至少具有来自大于第一延迟的端子的具有第二延迟的第二连接区域。 第一微电子元件（例如，半导体芯片）的地址输入可以与第一连接区域处的每个地址线耦合，并且第二微电子元件的地址输入可以在第二连接区域与每个地址线耦合 。

    Method for reduced load memory module
    9.
    发明授权
    Method for reduced load memory module 有权

    公开(公告)号：US10007622B2

    公开(公告)日：2018-06-26

    申请号：US15481288

    申请日：2017-04-06

    Applicant: Invensas Corporation

    Inventor： Zhuowen Sun ,  Yong Chen

    IPC: G06F13/16 ,  G11C8/12 ,  G06F12/06 ,  G11C5/06 ,  G11C8/06 ,  G11C5/04

    CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F12/0623 ,  G06F13/1694 ,  G11C5/04 ,  G11C5/06 ,  G11C8/06 ,  G11C8/12 ,  H01L2224/4824 ,  H01L2924/15311

    Abstract: A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

    Compact microelectronic assembly having reduced spacing between controller and memory packages
    10.
    发明授权
    Compact microelectronic assembly having reduced spacing between controller and memory packages 有权

    公开(公告)号：US09691437B2

    公开(公告)日：2017-06-27

    申请号：US14496159

    申请日：2014-09-25

    Applicant: Invensas Corporation

    Inventor： Zhuowen Sun ,  Yong Chen

    IPC: G11C5/06 ,  G11C5/02 ,  H01L23/00

    CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L24/00

    Abstract: A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.

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