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1.发明申请公开(公告)号：US20150050781A1
公开(公告)日：2015-02-19
申请号：US14529881
申请日：2014-10-31
IPC分类号： H01L23/00 , H01L21/56 , H01L21/768
CPC分类号： H01L24/11 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/768 , H01L23/315 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/26 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2221/68345 , H01L2224/03462 , H01L2224/0401 , H01L2224/11831 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/24227 , H01L2224/26 , H01L2224/27312 , H01L2224/2732 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/821 , H01L2224/83192 , H01L2224/83874 , H01L2224/92132 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/40252 , H01L2924/40407 , H01L2924/40501 , H05K1/185 , H05K3/4682 , H05K2201/10477 , H05K2203/0152 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
摘要翻译： 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。
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2.发明授权公开(公告)号：US08901724B2
公开(公告)日：2014-12-02
申请号：US12655335
申请日：2009-12-29
IPC分类号： H01L23/02 , H01L23/12 , H01L23/053 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/498 , H01L21/56 , H01L25/03 , H01L21/683 , H01L23/538 , H05K1/18 , H01L25/10 , H05K3/46 , H01L23/00
CPC分类号： H01L24/11 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/768 , H01L23/315 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/26 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2221/68345 , H01L2224/03462 , H01L2224/0401 , H01L2224/11831 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/24227 , H01L2224/26 , H01L2224/27312 , H01L2224/2732 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/821 , H01L2224/83192 , H01L2224/83874 , H01L2224/92132 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/40252 , H01L2924/40407 , H01L2924/40501 , H05K1/185 , H05K3/4682 , H05K2201/10477 , H05K2203/0152 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
摘要翻译： 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。
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3.发明申请公开(公告)号：US20110215464A1
公开(公告)日：2011-09-08
申请号：US12655335
申请日：2009-12-29
CPC分类号： H01L24/11 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/768 , H01L23/315 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/26 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2221/68345 , H01L2224/03462 , H01L2224/0401 , H01L2224/11831 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/24227 , H01L2224/26 , H01L2224/27312 , H01L2224/2732 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/821 , H01L2224/83192 , H01L2224/83874 , H01L2224/92132 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/40252 , H01L2924/40407 , H01L2924/40501 , H05K1/185 , H05K3/4682 , H05K2201/10477 , H05K2203/0152 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
摘要翻译： 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。
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公开(公告)号：US20100301492A1
公开(公告)日：2010-12-02
申请号：US12857332
申请日：2010-08-16
IPC分类号： H01L23/522
CPC分类号： H01L23/49822 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K1/0271 , H05K3/28 , H05K3/4682 , H05K2203/0582 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.
摘要翻译： 本发明的实施例涉及一种加强半导体无芯封装基板以提高刚性和抗翘曲性的方法。 该方法的一个实施例包括在无芯封装基板的第二级互连（封装 - 板间互连）侧上的多个接触焊盘上设置牺牲掩模，在牺牲掩模周围形成模制的加强件，而不增加有效厚度 并且去除牺牲掩模以在对应于接触焊盘的模制加强件中形成多个空腔。 实施例还包括用导电材料电镀接触垫的表面和模制空腔中的空腔的侧壁。
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公开(公告)号：US20100207265A1
公开(公告)日：2010-08-19
申请号：US12378953
申请日：2009-02-19
CPC分类号： H01L23/49822 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K1/0271 , H05K3/28 , H05K3/4682 , H05K2203/0582 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.
摘要翻译： 本发明的实施例涉及一种加强半导体无芯封装基板以提高刚性和抗翘曲性的方法。 该方法的一个实施例包括在无芯封装基板的第二级互连（封装 - 板间互连）侧上的多个接触焊盘上设置牺牲掩模，在牺牲掩模周围形成模制的加强件，而不增加有效厚度 并且去除牺牲掩模以在对应于接触焊盘的模制加强件中形成多个空腔。 实施例还包括用导电材料电镀接触垫的表面和模制空腔中的空腔的侧壁。
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公开(公告)号：US07851269B2
公开(公告)日：2010-12-14
申请号：US12378953
申请日：2009-02-19
IPC分类号： H01L21/00
CPC分类号： H01L23/49822 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K1/0271 , H05K3/28 , H05K3/4682 , H05K2203/0582 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.
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公开(公告)号：US08860205B2
公开(公告)日：2014-10-14
申请号：US12857332
申请日：2010-08-16
IPC分类号： H01L23/12 , H01L23/498 , H05K3/28 , H05K1/02 , H05K3/46
CPC分类号： H01L23/49822 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K1/0271 , H05K3/28 , H05K3/4682 , H05K2203/0582 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.
摘要翻译： 本发明的实施例涉及一种加强半导体无芯封装基板以提高刚性和抗翘曲性的方法。 该方法的一个实施例包括在无芯封装基板的第二级互连（封装 - 板间互连）侧上的多个接触焊盘上设置牺牲掩模，在牺牲掩模周围形成模制的加强件，而不增加有效厚度 并且去除牺牲掩模以在对应于接触焊盘的模制加强件中形成多个空腔。 实施例还包括用导电材料电镀接触垫的表面和模制空腔中的空腔的侧壁。
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公开(公告)号：US10446530B2
公开(公告)日：2019-10-15
申请号：US13977101
申请日：2011-08-16
IPC分类号： H05K1/11 , H05K3/40 , H01L25/18 , H01L23/498 , H01L23/00 , H01L25/10 , H01L21/48 , H01L25/00 , H01L25/065
摘要： An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
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9.发明申请OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES 审中-公开用于大型包装和大型包装包装结构的偏移插件公开(公告)号：US20130271907A1
公开(公告)日：2013-10-17
申请号：US13977101
申请日：2011-08-16
CPC分类号： H01L25/18 , H01L21/4846 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/43 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/89 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/08238 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48245 , H01L2224/48472 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/143 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1511 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/381 , H05K1/113 , H05K3/4038 , Y10T29/49124 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
摘要翻译： 偏移插入件包括包括陆侧侧球栅阵列（BGA）和包装袋（POP）侧的陆侧，该侧包括POP侧BGA。 接地侧BGA包括两个相邻的间隔开的陆侧焊盘，并且POP侧BGA包括两个相邻的间隔开的POP侧焊盘，其通过偏移插入件耦合到相应的两个焊盘侧BGA焊盘 。 地面BGA配置为与第一级互连进行接口POP侧BGA配置为与POP基板进行接口。 两个陆侧垫中的每一个具有与相应的两个POP侧垫不同的占地面积。
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公开(公告)号：US20110198723A1
公开(公告)日：2011-08-18
申请号：US13095317
申请日：2011-04-27
申请人： Todd B. Myers , Nicholas R. Watts , Eric C. Palmer , Jui Min Lim
发明人： Todd B. Myers , Nicholas R. Watts , Eric C. Palmer , Jui Min Lim
IPC分类号： H01L29/92
CPC分类号： H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
摘要翻译： 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。
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