公开(公告)号：US08569892B2

公开(公告)日：2013-10-29

申请号：US13062262

申请日：2009-10-05

申请人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

发明人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

IPC分类号： H01L23/48 ,  H01L23/10

CPC分类号： H01L24/85 ,  H01L23/13 ,  H01L23/142 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.

摘要翻译： 半导体器件包括：至少一个具有电极端子的半导体元件; 支撑半导体元件的金属板; 以及覆盖半导体元件并且在表面上交替堆叠的多个绝缘层和布线层以及外部连接端子的布线板，布线层通过通孔彼此电连接。 电极端子和外部连接端子经由布线层和通孔中的至少一个电连接。 至少一个电极端子，即布线层和通孔，电连接到金属板。

公开(公告)号：US20090283895A1

公开(公告)日：2009-11-19

申请号：US12446899

申请日：2007-10-09

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Masaya Kawano ,  Yuuji Kayashima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Masaya Kawano ,  Yuuji Kayashima

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/83 ,  H01L2224/82

摘要： A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.

摘要翻译： 一种半导体器件，包括具有穿透开口的金属框架; 设置在开口内的半导体芯片; 绝缘层，设置在金属框架的上表面上，使得绝缘层覆盖作为半导体芯片的电路形成表面的上表面; 互连层，其仅在金属框架的上表面侧设置，并且绝缘材料的介入并且电连接到半导体芯片的电路; 设置在所述半导体芯片的上表面上的通孔导体，以电连接半导体芯片的电路和互连层; 以及设置在金属框架的下表面上的树脂层。

公开(公告)号：US20120021357A1

公开(公告)日：2012-01-26

申请号：US13146841

申请日：2010-01-29

申请人： Katsumi Maeda ,  Shintaro Yamamichi

发明人： Katsumi Maeda ,  Shintaro Yamamichi

IPC分类号： G03F7/20 ,  G03F7/028

CPC分类号： G03F7/0392 ,  C08F220/30 ,  C08F220/58 ,  G03F7/0045

摘要： A photosensitive insulating resin composition, comprising a polymer, a photosensitizer, and an amide derivative that is expressed by the following general formula (1); (in formula (1), R1 represents a bivalent alkyl group, R2 represents a hydrocarbon group with a carbon number of 1 to 10, and R3 represents a hydrogen atom or an alkyl group with a carbon number of 1 to 4.)

摘要翻译： 一种感光绝缘树脂组合物，其包含由以下通式（1）表示的聚合物，光敏剂和酰胺衍生物; （式（1）中，R 1表示二价烷基，R 2表示碳数为1〜10的烃基，R 3表示氢原子或碳原子数为1〜4的烷基）

公开(公告)号：US08536691B2

公开(公告)日：2013-09-17

申请号：US12446899

申请日：2007-10-09

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Masaya Kawano ,  Yuuji Kayashima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Masaya Kawano ,  Yuuji Kayashima

IPC分类号： H01L23/02

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/83 ,  H01L2224/82

摘要： A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.

摘要翻译： 一种半导体器件，包括具有穿透开口的金属框架; 设置在开口内的半导体芯片; 绝缘层，设置在金属框架的上表面上，使得绝缘层覆盖作为半导体芯片的电路形成表面的上表面; 互连层，其仅在金属框架的上表面侧设置，并且绝缘材料的介入并且电连接到半导体芯片的电路; 设置在所述半导体芯片的上表面上的通孔导体，以电连接半导体芯片的电路和互连层; 以及设置在金属框架的下表面上的树脂层。

公开(公告)号：US20110175213A1

公开(公告)日：2011-07-21

申请号：US13062262

申请日：2009-10-05

申请人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

发明人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L23/13 ,  H01L23/142 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.

摘要翻译： 半导体器件包括：至少一个具有电极端子的半导体元件; 支撑半导体元件的金属板; 以及覆盖半导体元件并且在表面上交替堆叠的多个绝缘层和布线层以及外部连接端子的布线板，布线层通过通孔彼此电连接。 电极端子和外部连接端子经由布线层和通孔中的至少一个电连接。 至少一个电极端子，即布线层和通孔，电连接到金属板。

公开(公告)号：US20090001604A1

公开(公告)日：2009-01-01

申请号：US11817669

申请日：2006-03-01

申请人： Daisuke Tanaka ,  Shintaro Yamamichi ,  Hideya Murai ,  Tadanori Shimoto ,  Kaichirou Nakano ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Kouji Soejima

发明人： Daisuke Tanaka ,  Shintaro Yamamichi ,  Hideya Murai ,  Tadanori Shimoto ,  Kaichirou Nakano ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Kouji Soejima

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/00

摘要： An oxide layer and a metal layer composed of a gold- or platinum-group metal are formed in the stated order on a substrate. A wiring body having a wiring layer, insulating layer, via, and electrode is formed on the metal layer. A semiconductor element is then connected as a flip chip via solder balls on the wiring body electrode, and underfill is introduced between the semiconductor element and the wiring body. Subsequently, a sealing resin layer is formed so as to cover the semiconductor element and the surface of the wiring body on which the semiconductor element is mounted, thus producing a semiconductor package. A high-density, detailed, thin semiconductor package can thereby be realized.

摘要翻译： 在基板上按规定的顺序形成由金或铂族金属构成的氧化物层和金属层。 具有布线层，绝缘层，通孔和电极的布线体形成在金属层上。 然后，半导体元件作为倒装芯片通过布线体电极上的焊球连接，底部填充物被引入到半导体元件与布线体之间。 随后，形成密封树脂层，以覆盖半导体元件和安装有半导体元件的布线体的表面，从而制造半导体封装。 由此可以实现高密度，详细，薄的半导体封装。

公开(公告)号：US08815678B2

公开(公告)日：2014-08-26

申请号：US11928460

申请日：2007-10-30

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L21/8242 ,  H01L21/316 ,  H01L49/02 ,  C23C16/455 ,  G11C11/404 ,  H01L21/314 ,  H01L27/108 ,  C23C16/40

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US08212299B2

公开(公告)日：2012-07-03

申请号：US10170813

申请日：2002-06-13

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1−x)O2(0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US20120119338A1

公开(公告)日：2012-05-17

申请号：US13200944

申请日：2011-10-05

申请人： Takahito Watanabe ,  Shintaro Yamamichi ,  Yoshitaka Ushiyama

发明人： Takahito Watanabe ,  Shintaro Yamamichi ,  Yoshitaka Ushiyama

IPC分类号： H01L23/552 ,  H01L21/02

CPC分类号： H01L23/58 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/552 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/97 ,  H01L27/224 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2916 ,  H01L2224/2919 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/1435 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

摘要翻译： 半导体芯片包括磁存储装置，并且在第一面上包括电极焊盘。 至少在电极焊盘露出的状态下，半导体芯片被覆有磁屏蔽层。 半导体芯片通过凸块安装在互连基板上。 半导体芯片和互连基板中的至少一个包括凸部，并且凸块设置在凸部上。

公开(公告)号：US08169013B2

公开(公告)日：2012-05-01

申请号：US11637147

申请日：2006-12-12

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0

摘要翻译： 一种具有形成在同一半导体芯片上的逻辑部分和存储部分的半导体器件，包括：形成在逻辑部分中并具有栅电极和源极和漏极区域的第一晶体管，以及形成在存储部分中的第二晶体管， 栅极电极，源极和漏极区域以及电容器，电容器是MIM结构，并且具有夹在其间的上部和下部金属电极和电容器电介质膜，所述电容器电介质膜由介电材料形成，所述绝缘材料选自 由ZrO2，Hf92，（Zrx，Hf1-x）O2（0