公开(公告)号：US07483818B2

公开(公告)日：2009-01-27

申请号：US10157926

申请日：2002-05-31

申请人： Makoto Amakai ,  Iwao Sugiura ,  Takanori Negishi ,  Yasuhiro Kawashima ,  Gen Kamurai ,  Kazuyuki Imamura

发明人： Makoto Amakai ,  Iwao Sugiura ,  Takanori Negishi ,  Yasuhiro Kawashima ,  Gen Kamurai ,  Kazuyuki Imamura

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5018

摘要： A structural analysis program which enables easy structural analysis in accordance with a finite element method based on data representing a two-dimensional shape. A two-dimensional model of a structure is produced in response to a manipulation input which designates a material arrangement pattern and a thickness of each layer of the structure. A three-dimensional model is produced by adding the designated thickness of each layer to the material arrangement pattern of the layer so as to make the material arrangement pattern three-dimensional and stacking the three-dimensionalized material arrangement pattern of each layer. A finite element model is produced by dividing the three-dimensional model into a plurality of voxels. The computer performs structural analysis based on the produced finite element model. Thereby, an analysis result of a multilayer structure defined by the two-dimensional model is obtained.

摘要翻译： 一种结构分析程序，其能够根据基于表示二维形状的数据的有限元方法进行容易的结构分析。 响应于指定结构的每个层的材料布置图案和厚度的操作输入而产生结构的二维模型。 通过将各层的指定厚度添加到层的材料布置图案以使三维材料布置图案和每层的三维化材料排列图案堆叠来生成三维模型。 通过将三维模型划分成多个体素来产生有限元模型。 计算机根据生产的有限元模型进行结构分析。 由此，得到由二维模型定义的多层结构的分析结果。

公开(公告)号：US06566748B1

公开(公告)日：2003-05-20

申请号：US09615728

申请日：2000-07-13

申请人： Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Masaharu Minamizawa

发明人： Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Masaharu Minamizawa

IPC分类号： H01L2312

CPC分类号： H01L23/06 ,  H01L21/563 ,  H01L23/04 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19105

摘要： A BGA semiconductor device includes a package substrate carrying thereon a semiconductor chip in a face-down state and a cap member covering the semiconductor chip on the package substrate, wherein the cap member has a optimized Young modulus smaller than about 20 GPa and a thermal conductivity exceeding about 100 W/(m·K).

摘要翻译： BGA半导体器件包括在其上承载有面朝下状态的半导体芯片的封装基板和覆盖封装基板上的半导体芯片的盖构件，其中该盖构件具有小于约20GPa的优化的杨氏模量和导热系数 超过100W /（mK）。

公开(公告)号：US20100155941A1

公开(公告)日：2010-06-24

申请号：US12690469

申请日：2010-01-20

申请人： Hirohisa Matsuki ,  Kazuyuki Imamura

发明人： Hirohisa Matsuki ,  Kazuyuki Imamura

IPC分类号： H01L23/498

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49894 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105

摘要： A semiconductor device includes multiple electrode pads provided in an interconnection layer over a semiconductor substrate; an insulating layer provided on the interconnection layer so as to expose portions of the electrode pads; multiple conductive layers having their respective first ends connected to the exposed portions of the corresponding electrode pads so as to extend therefrom on the insulating layer; and multiple protruding electrodes provided at respective second ends of the conductive layers, wherein the conductive layers extend in a given direction relative to the electrode pads.

摘要翻译： 半导体器件包括设置在半导体衬底上的互连层中的多个电极焊盘; 绝缘层，设置在所述互连层上以暴露所述电极焊盘的部分; 多个导电层，其各自的第一端连接到相应的电极焊盘的暴露部分，从而在绝缘层上延伸; 以及设置在所述导电层的相应第二端处的多个突出电极，其中所述导电层相对于所述电极焊盘沿给定方向延伸。

公开(公告)号：US5627911A

公开(公告)日：1997-05-06

申请号：US300219

申请日：1994-09-06

申请人： Yoshikazu Inumaru ,  Kazuyuki Imamura

发明人： Yoshikazu Inumaru ,  Kazuyuki Imamura

IPC分类号： H04N7/18 ,  G06K9/20 ,  G06T1/00 ,  G06T7/00 ,  G06K9/00

CPC分类号： G06K9/033 ,  G06K9/036 ,  G06K9/20 ,  G06T7/0004 ,  G06T2207/10016 ,  G06T2207/30108

摘要： An article under inspection is rotated at pre-set angular increments which total more than 360.degree., to divide the figure inscribed on the curved surface of the article into plural fractions. Selected picture fractions which discard redundant overlapping picture data, is synthesized into picture information indicative of one full-format picture based on which the figure inscribed on the curved surface of the article. Acceptability is determined automatically and quantitatively as compared to the conventional functional inspection and is performed without regard to the difference in skill from one operator to another. Recognizing the characters or symbols inscribed on the curved surface of the article under inspection one by one based on the information of the synthesized full-format picture, allows a comparison of the character string consisting of the recognized characters or symbols to a pre-set control character string.

摘要翻译： 被检查的物品以预先设定的角度增量旋转，总共大于360度，将制品的弯曲表面上划出的图形分成多个部分。 将丢弃冗余重叠图像数据的所选择的图像分数合成为指示一个全格式图像的图像信息，根据该图像内容刻在物品的曲面上。 与常规功能检查相比，可自动和定量地确定可接受性，并且在不考虑从一个操作者到另一个操作员的技能差异的情况下执行可接受性。 基于合成的全格式图像的信息，识别被检查物品的曲面上刻有的字符或符号，允许将由识别的字符或符号组成的字符串与预设控制进行比较 字符串。

公开(公告)号：US07754534B2

公开(公告)日：2010-07-13

申请号：US12081723

申请日：2008-04-21

申请人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H01L21/00

CPC分类号： H01L21/6836 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75315 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

摘要翻译： 提供一种使用布线基板制造半导体器件的方法，其可以有助于布线基板的处理。 该方法包括以下步骤：在硅基板上形成可剥离树脂层，在可剥离树脂层上形成布线基板，在布线基板上安装半导体芯片，通过密封树脂密封多个半导体芯片形成半导体器件， 半导体器件通过从密封树脂侧切割半导体器件但离开硅衬底，从硅衬底和可剥离树脂层之间的硅衬底剥离每个单独的半导体器件，并且通过形成开口 通过可剥离树脂层或通过除去可剥离树脂层。

公开(公告)号：US07268433B2

公开(公告)日：2007-09-11

申请号：US11256273

申请日：2005-10-24

申请人： Yoshihiro Matsuoka ,  Kazuyuki Imamura ,  Masao Oshima ,  Takashi Suzuki ,  Toyoji Sawada

发明人： Yoshihiro Matsuoka ,  Kazuyuki Imamura ,  Masao Oshima ,  Takashi Suzuki ,  Toyoji Sawada

IPC分类号： H01L23/482 ,  H01L23/485

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05011 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2924/00014

摘要： A wiring layer is provided on a semiconductor substrate and extends in a predetermined direction. An external connection electrode terminal is provided on the wiring layer through a plurality of column-shaped conductors. The column-shaped conductors are located under the external connection electrode terminal. A density of arrangement of the column-shaped conductors is varied according to a direction of extension of the wiring layer.

摘要翻译： 布线层设置在半导体基板上并沿预定方向延伸。 外部连接电极端子通过多个列状导体设置在布线层上。 柱状导体位于外部连接电极端子的下方。 柱状导体的排列密度根据布线层的延伸方向而变化。

公开(公告)号：US20070001317A1

公开(公告)日：2007-01-04

申请号：US11256273

申请日：2005-10-24

申请人： Yoshihiro Matsuoka ,  Kazuyuki Imamura ,  Masao Oshima ,  Takashi Suzuki ,  Toyoji Sawada

发明人： Yoshihiro Matsuoka ,  Kazuyuki Imamura ,  Masao Oshima ,  Takashi Suzuki ,  Toyoji Sawada

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05011 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2924/00014

摘要： A wiring layer is provided on a semiconductor substrate and extends in a predetermined direction. An external connection electrode terminal is provided on the wiring layer through a plurality of column-shaped conductors. The column-shaped conductors are located under the external connection electrode terminal. A density of arrangement of the column-shaped conductors is varied according to a direction of extension of the wiring layer.

公开(公告)号：US06476503B1

公开(公告)日：2002-11-05

申请号：US09606196

申请日：2000-06-29

申请人： Kazuyuki Imamura ,  Yasunori Fujimoto ,  Masaaki Seki ,  Tetsuya Fujisawa ,  Mitsutaka Sato ,  Ryuji Nomoto ,  Junichi Kasai ,  Yoshitaka Aiba ,  Noriaki Shiba

发明人： Kazuyuki Imamura ,  Yasunori Fujimoto ,  Masaaki Seki ,  Tetsuya Fujisawa ,  Mitsutaka Sato ,  Ryuji Nomoto ,  Junichi Kasai ,  Yoshitaka Aiba ,  Noriaki Shiba

IPC分类号： H01L2348

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/12105 ,  H01L2224/13011 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147

摘要： A semiconductor device including a semiconductor chip sealed with an encapsulating resin. Columnar electrodes are connected to electrode pads of the semiconductor chip, and extend through the encapsulating resin. The columnar electrodes are made from bonding wires and include enlarged outer ends. Solder balls are arranged on the surface of the encapsulating resin and connected to the outer ends of the columnar electrodes. In another example, pin wires are formed by half-cutting bonding wires, bonding one end of each of the bonding wires, and cutting the bonding wires at the half-cut portions.

摘要翻译： 一种半导体器件，包括用封装树脂密封的半导体芯片。 柱状电极连接到半导体芯片的电极焊盘，并且延伸穿过封装树脂。 柱状电极由接合线制成，并且包括扩大的外端。 焊球布置在封装树脂的表面上并连接到柱状电极的外端。 在另一个例子中，通过半切割接合线，接合每个接合线的一端，以及在半切部分切割接合线来形成引线。

公开(公告)号：US06232147B1

公开(公告)日：2001-05-15

申请号：US09365413

申请日：1999-08-02

申请人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

发明人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/013

摘要： A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property. The semiconductor device has: semiconductor circuit elements 2 embedded in a semiconductor substrate 1; a plurality of conductive primary pads 4 each formed in a region above, and surrounding, the circuit element 2; a first protective insulation substrate 5 covering the substrate and having first openings 6 for the primary pads 4; lead wires 7 each consisting of a conductive bulk layer 15 made of copper and a metallic top layer 16, the bulk layer formed on the first protective insulation substrate 5 and having one end connected with a corresponding one of the primary pads 4 through an associated opening 6 and the other end located in a region surrounding the opening 6, while the top layer made of a metal having Vickers hardness of more than 100; and a second protective insulation substrate 8 having second openings 9 for exposing the top surfaces of the other ends of the lead wires 7 serving as the secondary pads 17.

摘要翻译： 一种装备有用于任意包装过程的适当布置的辅助垫的半导体器件。 辅助焊盘与半导体器件的主焊盘与新颖的引线结构连接，其特征在于其低电阻，良好的机械强度以保护器件的有源部件，对凸块的良好粘附性和抗电迁移性 。 半导体器件具有：嵌入半导体衬底1中的半导体电路元件2; 多个导电性主焊盘4，各自形成在电路元件2的上方并包围电路元件2的区域中; 覆盖基板并具有用于主焊盘4的第一开口6的第一保护绝缘基板5; 引线7由导电体层15和铜构成，金属顶层16形成在第一保护绝缘基片5上，并且其一端通过相关的开口连接到相应的一个主焊盘4中 6，另一端位于围绕开口6的区域中，而顶层由维氏硬度大于100的金属制成; 以及具有第二开口9的第二保护绝缘基板8，用于暴露作为二次焊盘17的引线7的另一端的顶表面。

公开(公告)号：US5969424A

公开(公告)日：1999-10-19

申请号：US999115

申请日：1997-12-29

申请人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

发明人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

IPC分类号： H01L23/485 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181

摘要： A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property. The semiconductor device has: semiconductor circuit elements 2 embedded in a semiconductor substrate 1; a plurality of conductive primary pads 4 each formed in a region above, and surrounding, the circuit element 2; a first protective insulation substrate 5 covering the substrate and having first openings 6 for the primary pads 4; lead wires 7 each consisting of a conductive bulk layer 15 made of copper and a metallic top layer 16, the bulk layer formed on the first protective insulation substrate 5 and having one end connected with a corresponding one of the primary pads 4 through an associated opening 6 and the other end located in a region surrounding the opening 6, while the top layer made of a metal having Vickers hardness of more than 100; and a second protective insulation substrate 8 having second openings 9 for exposing the top surfaces of the other ends of the lead wires 7 serving as the secondary pads 17.

摘要翻译： 一种装备有用于任意包装过程的适当布置的辅助垫的半导体器件。 辅助焊盘与半导体器件的主焊盘与新颖的引线结构连接，其特征在于其低电阻，良好的机械强度以保护器件的有源部件，对凸块的良好粘附性和抗电迁移性 。 半导体器件具有：嵌入半导体衬底1中的半导体电路元件2; 多个导电性主焊盘4，各自形成在电路元件2的上方并包围电路元件2的区域中; 覆盖基板并具有用于主焊盘4的第一开口6的第一保护绝缘基板5; 引线7由导电体层15和铜构成，金属顶层16形成在第一保护绝缘基片5上，并且其一端通过相关的开口连接到相应的一个主焊盘4中 6，另一端位于围绕开口6的区域中，而顶层由维氏硬度大于100的金属制成; 以及具有第二开口9的第二保护绝缘基板8，用于暴露作为二次焊盘17的引线7的另一端的顶表面。