公开(公告)号：US06476503B1

公开(公告)日：2002-11-05

申请号：US09606196

申请日：2000-06-29

申请人： Kazuyuki Imamura ,  Yasunori Fujimoto ,  Masaaki Seki ,  Tetsuya Fujisawa ,  Mitsutaka Sato ,  Ryuji Nomoto ,  Junichi Kasai ,  Yoshitaka Aiba ,  Noriaki Shiba

发明人： Kazuyuki Imamura ,  Yasunori Fujimoto ,  Masaaki Seki ,  Tetsuya Fujisawa ,  Mitsutaka Sato ,  Ryuji Nomoto ,  Junichi Kasai ,  Yoshitaka Aiba ,  Noriaki Shiba

IPC分类号： H01L2348

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/12105 ,  H01L2224/13011 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147

摘要： A semiconductor device including a semiconductor chip sealed with an encapsulating resin. Columnar electrodes are connected to electrode pads of the semiconductor chip, and extend through the encapsulating resin. The columnar electrodes are made from bonding wires and include enlarged outer ends. Solder balls are arranged on the surface of the encapsulating resin and connected to the outer ends of the columnar electrodes. In another example, pin wires are formed by half-cutting bonding wires, bonding one end of each of the bonding wires, and cutting the bonding wires at the half-cut portions.

摘要翻译： 一种半导体器件，包括用封装树脂密封的半导体芯片。 柱状电极连接到半导体芯片的电极焊盘，并且延伸穿过封装树脂。 柱状电极由接合线制成，并且包括扩大的外端。 焊球布置在封装树脂的表面上并连接到柱状电极的外端。 在另一个例子中，通过半切割接合线，接合每个接合线的一端，以及在半切部分切割接合线来形成引线。

公开(公告)号：US06333564B1

公开(公告)日：2001-12-25

申请号：US09336747

申请日：1999-06-21

申请人： Yoshitsugu Katoh ,  Mitsutaka Sato ,  Hiroshi Inoue ,  Seiichi Orimo ,  Akira Okada ,  Yoshihiro Kubota ,  Mitsuo Abe ,  Toshio Hamano ,  Yoshitaka Aiba ,  Tetsuya Fujisawa ,  Masaaki Seki ,  Noriaki Shiba

发明人： Yoshitsugu Katoh ,  Mitsutaka Sato ,  Hiroshi Inoue ,  Seiichi Orimo ,  Akira Okada ,  Yoshihiro Kubota ,  Mitsuo Abe ,  Toshio Hamano ,  Yoshitaka Aiba ,  Tetsuya Fujisawa ,  Masaaki Seki ,  Noriaki Shiba

IPC分类号： H01L2348

CPC分类号： H01L23/3107 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device and a method of producing the same, the device including a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between the substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for the holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.

摘要翻译： 一种半导体器件及其制造方法，该器件包括半导体芯片; 作为外部连接端子的球; 电连接半导体芯片和滚珠的基板; 模制树脂，其密封半导体芯片的至少一部分; 以及密封基板和半导体芯片之间的连接部分的连接部密封树脂。 半导体器件通过球安装到印刷电路板上。 模制树脂的热膨胀系数与印刷电路板的热膨胀系数相匹配。 在模制树脂中形成用于保持半导体芯片的侧表面的侧表面保持部分，以限制半导体芯片的热变形。

公开(公告)号：US20060040532A1

公开(公告)日：2006-02-23

申请号：US11019156

申请日：2004-12-23

申请人： Kaname Ozawa ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshiyuki Yoneda ,  Ryuji Nomoto ,  Yoshitaka Aiba

发明人： Kaname Ozawa ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshiyuki Yoneda ,  Ryuji Nomoto ,  Yoshitaka Aiba

IPC分类号： H01R13/648

CPC分类号： G06F17/5068 ,  H05K3/0005

摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.

摘要翻译： 一种能够高效率地绘制高密度导线的电路板的设计方法。 大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。 然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。 然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。 如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导线，则通过设定的规则布置其余区域的导体线。

公开(公告)号：US07251801B2

公开(公告)日：2007-07-31

申请号：US11019156

申请日：2004-12-23

申请人： Kaname Ozawa ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshiyuki Yoneda ,  Ryuji Nomoto ,  Yoshitaka Aiba

发明人： Kaname Ozawa ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshiyuki Yoneda ,  Ryuji Nomoto ,  Yoshitaka Aiba

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H05K3/0005

摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.

摘要翻译： 一种能够高效率地绘制高密度导线的电路板的设计方法。 大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。 然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。 然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。 如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导体线，则通过设定的规则布置其余区域的导体线。

公开(公告)号：US06836025B2

公开(公告)日：2004-12-28

申请号：US10448444

申请日：2003-05-30

申请人： Tetsuya Fujisawa ,  Hirohisa Matsuki ,  Osamu Igawa ,  Yoshitaka Aiba ,  Masamitsu Ikumo ,  Mitsutaka Sato

发明人： Tetsuya Fujisawa ,  Hirohisa Matsuki ,  Osamu Igawa ,  Yoshitaka Aiba ,  Masamitsu Ikumo ,  Mitsutaka Sato

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/24265 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

摘要翻译： 在半导体器件中，当半导体芯片并排布置时，多个半导体芯片中的每一个的形成表面可以容易地位于均匀的水平，从而简化了布置布线的处理。 半导体芯片通过二维布置的粘合剂层安装在基板上。 树脂层形成在基板上并位于半导体元件周围。 树脂层的厚度与半导体元件的厚度相同。 在树脂层的表面和半导体元件的电路形成表面上形成有机绝缘层。 在有机绝缘层和半导体芯片的电极上形成重排布线层。 外部连接端子通过布线布线层中的布线电连接到半导体元件的电路形成表面。

公开(公告)号：US5842628A

公开(公告)日：1998-12-01

申请号：US628936

申请日：1996-04-08

申请人： Ryuji Nomoto ,  Kazuto Tsuji ,  Mitsutaka Sato ,  Junichi Kasai

发明人： Ryuji Nomoto ,  Kazuto Tsuji ,  Mitsutaka Sato ,  Junichi Kasai

IPC分类号： B23K20/00 ,  H01L21/607 ,  B23K31/02

CPC分类号： H01L24/85 ,  B23K20/004 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  B23K2201/40 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49109 ,  H01L2224/4945 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85009 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85191 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L24/45 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181

摘要： A wire bonding method includes a first bonding process for forming a first ball-shaped part in a wire and bonding the first ball-shaped part to a first connected member; a ball-shaped part forming process for guiding the wire away from a position where the wire is bonded to an inner lead so as to form a predetermined loop, and forming a second ball-shaped part in a predetermined position in the wire; and a second bonding process for bonding the second ball-shaped part to a semiconductor element pad that serves as a second connected member.

摘要翻译： 引线接合方法包括用于在线中形成第一球形部分并将第一球形部分接合到第一连接部件的第一接合工艺; 一种用于将线材从导线接合的位置引导到内部引线以形成预定环路的滚珠形部分形成工艺，并且在线材中的预定位置形成第二球形部分; 以及用于将第二球形部件接合到用作第二连接部件的半导体元件衬垫的第二接合工艺。

公开(公告)号：US06784543B2

公开(公告)日：2004-08-31

申请号：US10374965

申请日：2003-02-28

申请人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

发明人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC分类号： H01L2352

CPC分类号： H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

摘要翻译： 其中磷镍层，含有比该磷 - 镍层高的​​磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是 在电极上依次形成。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

公开(公告)号：US06495773B1

公开(公告)日：2002-12-17

申请号：US09160536

申请日：1998-09-25

申请人： Ryuji Nomoto ,  Kazuto Tsuji ,  Mitsutaka Sato ,  Junichi Kasai

发明人： Ryuji Nomoto ,  Kazuto Tsuji ,  Mitsutaka Sato ,  Junichi Kasai

IPC分类号： H05K116

CPC分类号： H01L24/85 ,  B23K20/004 ,  B23K2101/40 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49109 ,  H01L2224/4945 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85009 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85191 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399

摘要： A wire bonding method includes a first bonding process for forming a first ball-shaped part in a wire and bonding the first ball-shaped part to a first connected member; a ball-shaped part forming process for guiding the wire away from a position where the wire is bonded to an inner lead so as to form a predetermined loop, and a second bonding process for forming a second ball-shaped part in a predetermined position in the wire; and a second bonding process for bonding the second ball-shaped part to a semiconductor element pad that serves as a second connected member.

摘要翻译： 引线接合方法包括用于在线中形成第一球形部分并将第一球形部分接合到第一连接部件的第一接合工艺; 一种用于将线材从导线接合的位置引导到内部引线以形成预定的环路的滚珠形部分形成工艺，以及用于在预定位置形成第二球形部件的第二接合工艺 电线; 以及用于将第二球形部件接合到用作第二连接部件的半导体元件衬垫的第二接合工艺。

公开(公告)号：US06548898B2

公开(公告)日：2003-04-15

申请号：US09895330

申请日：2001-07-02

申请人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

发明人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC分类号： H01L2352

CPC分类号： H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

摘要翻译： 其中磷镍层，含有比该磷 - 镍层高的​​磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是 在电极上依次形成。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

公开(公告)号：US06696754B2

公开(公告)日：2004-02-24

申请号：US10214306

申请日：2002-08-08

申请人： Mitsutaka Sato ,  Tetsuya Fujisawa ,  Shigeyuki Maruyama ,  Junichi Kasai ,  Toshimi Kawahara ,  Toshio Hamano ,  Yoshihiro Kubota ,  Mitsunada Osawa ,  Yoshiyuki Yoneda ,  Kazuto Tsuji ,  Hirohisa Matsuki

发明人： Mitsutaka Sato ,  Tetsuya Fujisawa ,  Shigeyuki Maruyama ,  Junichi Kasai ,  Toshimi Kawahara ,  Toshio Hamano ,  Yoshihiro Kubota ,  Mitsunada Osawa ,  Yoshiyuki Yoneda ,  Kazuto Tsuji ,  Hirohisa Matsuki

IPC分类号： H01L2334

CPC分类号： H01L25/105 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2924/09701 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/82 ,  H05K7/1431 ,  H01L2924/00

摘要： A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.

摘要翻译： 半导体模块包括多个半导体器件，每个半导体器件包括承载有单个存储器半导体芯片的电路衬底和用于可拆卸地保持半导体器件的插座。