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80 条记录 (耗时 0.021 秒)

    Method of making mask pattern data and process for manufacturing the mask
    7.
    发明授权
    Method of making mask pattern data and process for manufacturing the mask 失效
    制作掩模图案数据的方法和用于制造掩模的工艺

    公开(公告)号：US5458998A

    公开(公告)日：1995-10-17

    申请号：US886403

    申请日：1992-05-21

    申请人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

    发明人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

    IPC分类号： G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  G03F1/84 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

    CPC分类号： G03F1/26 ,  G03F1/29 ,  G03F1/84

    摘要： Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (108) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

    摘要翻译： 可以检查相移掩模的图案数据：（101）通过在实际图案数据层，辅助图案数据层和相移图案数据层中分离和布置相移掩模的图案数据; （102），通过检查和校正实际图案数据层的实际图案的数据; （108）通过从被检查和校正的正确的实际图案数据，辅助图案数据和相移图案数据的合成数据的数据中制作估计传送到半导体晶片的估计图案的数据; 和（104）通过比较估计的图案数据和实际图案数据来检查辅助图案和相移图案的数据。

    Semiconductor memory having multiple continuous access functions
    8.
    发明授权
    Semiconductor memory having multiple continuous access functions 失效
    具有多个连续访问功能的半导体存储器

    公开(公告)号：US4802135A

    公开(公告)日：1989-01-31

    申请号：US902564

    申请日：1986-09-02

    申请人： Takashi Shinoda ,  Masamichi Ishihara

    发明人： Takashi Shinoda ,  Masamichi Ishihara

    IPC分类号： G11C11/34 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/408 ,  G11C11/40 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1021 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C8/18

    摘要： A pseudo static RAM is provided which uses a one MOSFET dynamic RAM cell, in which two functions of a page mode and a static column mode are realized by using an address buffer having a function to transmit address signals fed from external terminals as they are and a latch function to latch the address signals fed from the external terminals in synchronism with predetermined control signals fed from the external terminals. The address buffer also has a multiplexer function to selectively incorporate the address signals from the external terminals and the address signals produced in the inside of the RAM so that the address buffer and an internal address signal generating circuit may be controlled by external control terminals to make possible the continuous access by the internal address signals.

    摘要翻译： 提供了一种伪静态RAM，其使用一个MOSFET动态RAM单元，其中通过使用具有从外部端子原样馈送的地址信号的功能的地址缓冲器来实现页面模式和静态列模式的两个功能，以及 锁存功能，用于与从外部端子馈送的预定控制信号同步地锁存从外部端子馈送的地址信号。 地址缓冲器还具有多路复用功能，用于选择性地并入来自外部端子的地址信号和在RAM内部产生的地址信号，使得地址缓冲器和内部地址信号发生电路可以由外部控制端子控制， 可能通过内部地址信号的连续访问。

    Heat sink package and method of manufacturing
    9.
    发明授权
    Heat sink package and method of manufacturing 有权
    散热片包装及制造方法

    公开(公告)号：US08988882B2

    公开(公告)日：2015-03-24

    申请号：US13259563

    申请日：2010-03-24

    申请人： Kenji Ohsawa ,  Rinkou Fukunaga ,  Katsuya Tsuruta ,  Kei Mizuta ,  Masamichi Ishihara

    发明人： Kenji Ohsawa ,  Rinkou Fukunaga ,  Katsuya Tsuruta ,  Kei Mizuta ,  Masamichi Ishihara

    IPC分类号： H05K7/20 ,  H01L23/498 ,  H01L23/367 ,  H01L23/433 ,  H05K1/00 ,  H01L21/48

    CPC分类号： H01L23/49816 ,  H01L21/4867 ,  H01L23/367 ,  H01L23/4334 ,  H01L2224/16225 ,  H01L2924/15321 ,  Y10T29/4913

    摘要： A circuit element is arranged on an organic substrate and connected to a wiring pattern arranged on the organic substrate. An internal connection electrode is formed on a conductive support body by electroforming so as to obtain a unitary block of the internal connection electrode and the support body. Each end of each of the internal connection electrodes connected into a unitary block by the support body is connected to the wiring pattern. After the circuit element is sealed by resin, the support body is peeled off, so as to obtain individual internal connection electrodes separately and the other end of each of the internal connection electrodes is used as an external connection electrode on the front surface while the external connection electrode on the rear surface is connected to the wiring pattern.

    摘要翻译： 电路元件设置在有机基板上并连接到布置在有机基板上的布线图案。 通过电铸在导电性支撑体上形成内部连接电极，以获得内部连接电极和支撑体的整体块。 通过支撑体连接到整体块的每个内部连接电极的每个端部连接到布线图案。 在电路元件被树脂密封之后，剥离支撑体，以分别获得单独的内部连接电极，并且将每个内部连接电极的另一端用作前表面上的外部连接电极，而外部 后表面上的连接电极连接到布线图案。