公开(公告)号：US20070281393A1

公开(公告)日：2007-12-06

申请号：US11421006

申请日：2006-05-30

申请人： Viswanadam Gautham ,  Lan Chu Tan ,  Heng Keong Yip

发明人： Viswanadam Gautham ,  Lan Chu Tan ,  Heng Keong Yip

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of forming a semiconductor package (32) includes etching a conductive sheet (10) to form a first interconnection system (12). An integrated circuit (IC) die (22) is placed on and electrically connected to the first interconnection system (12). Next, a molding operation is performed to encapsulate the IC die (22), the electrical connections (24, 26) and at least a portion of the first interconnection system (12). A portion (20) of the conductive sheet (10) is then removed to expose a surface (30) of the first interconnection system (12). A second interconnection system (34) then is formed over the exposed surface (30) of the first interconnection system (12).

摘要翻译： 形成半导体封装（32）的方法包括蚀刻导电片（10）以形成第一互连系统（12）。 集成电路（IC）管芯（22）放置在电连接到第一互连系统（12）上。 接下来，执行模制操作以封装IC管芯（22），电连接（24,26）和第一互连系统（12）的至少一部分。 然后去除导电片（10）的一部分（20）以暴露第一互连系统（12）的表面（30）。 然后在第一互连系统（12）的暴露表面（30）上形成第二互连系统（34）。

公开(公告)号：US07160798B2

公开(公告)日：2007-01-09

申请号：US11065360

申请日：2005-02-24

申请人： Viswanadam Gautham ,  Lan Chu Tan

发明人： Viswanadam Gautham ,  Lan Chu Tan

IPC分类号： H01L21/4763

CPC分类号： H01L23/49861 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of making a reinforced semiconductor package includes forming a semiconductor interconnect tablet (24). Formation of the tablet includes providing a plurality of conductive metal tabs (10), positioning a first end (12) of the tabs (10) in a first section of a mold chase (14), positioning a second section of the mold chase (16) over a second end (18) of the tabs (10), such that the tabs (10) are anchored between the first and second sections (14, 16) of the mold chase, loading the first and second sections (14, 16) of the mold chase into a molding system (20) and performing a molding operation such that a plastic mold compound (22) is formed around the metal tabs (10) and an interconnect tablet (24) is formed. Then the first and second sections (14, 16) of the mold chase are removed from the molding system (20) and the interconnect tablet (24) is removed from the first and second sections (14, 16) of the mold chase.

摘要翻译： 制造增强半导体封装的方法包括形成半导体互连片（24）。 片剂的形成包括提供多个导电金属片（10），将突片（10）的第一端（12）定位在模具追逐（14）的第一部分中，定位模具追逐的第二部分（ （10）的第二端（18）上，使得突片（10）锚定在模具追逐的第一和第二部分（14,16）之间，将第一和第二部分（14， 16）模制成模制系统（20），并执行模制操作，使得在金属薄片（10）周围形成塑料模具化合物（22），形成互连薄片（24）。 然后将模具追逐的第一和第二部分（14,16）从模制系统（20）中移除，并且互连片（24）从模具追逐的第一和第二部分（14,16）移除。

公开(公告)号：US20160064356A1

公开(公告)日：2016-03-03

申请号：US14474294

申请日：2014-09-01

申请人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/03602 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L21/565 ,  H01L21/304 ,  H01L2224/83

摘要： A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

摘要翻译： 制造诸如球栅阵列的集成电路封装的方法包括提供在其相应的第一和第二表面上具有第一组和第二组接合焊盘的柔性带。 载体附接到柔性带的第一表面。 然后在第二组接合焊盘上形成导电柱，并且在柔性带的第二表面上沉积聚合物化合物的中间层。 在化合物固化之后，研磨中间层的表面以暴露导电柱的端部以形成包括柔性带和中间层的子组件。 然后从子组件移除载体，从而形成插入件。 插入器附接到衬底，并且至少一个管芯附接到插入器。

公开(公告)号：US08853058B2

公开(公告)日：2014-10-07

申请号：US13530117

申请日：2012-06-22

申请人： Kesvakumar V. C. Muniandy ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Kesvakumar V. C. Muniandy ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L21/568 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/3735 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00

摘要： A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.

摘要翻译： 一种组装半导体器件的方法包括提供一种结构，其包括除了孔阵列之外的导电框架构件的阵列和在第一面处暴露并朝向第二面延伸的导电通孔阵列。 一组半导体管芯位于孔阵列中，其主动面位于结构的第一面。 组件从结构的第二面被封装，并且在结构的第一面和模具的有效面上形成再分布层。 从封装阵列的背面去除材料以暴露在背面的通孔，用于通过形成在背面上的另一重新分配层与垂直堆叠在再分布层上的电子部件连接。

公开(公告)号：US20140206124A1

公开(公告)日：2014-07-24

申请号：US14219011

申请日：2014-03-19

申请人： Jinzhong Yao ,  Wai Yew Lo ,  Lan Chu Tan ,  Xuesong Xu

发明人： Jinzhong Yao ,  Wai Yew Lo ,  Lan Chu Tan ,  Xuesong Xu

IPC分类号： H01L41/25

CPC分类号： H01L41/25 ,  G01L19/0069 ,  G01L19/147 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.

摘要翻译： 包装压力传感器管芯的方法包括提供引线框架，其具有围绕管芯焊盘的管芯焊盘和引线指。 带子附接到引线框架的第一侧。 压力传感器芯片在引线框架的第二侧附接到芯片焊盘，并且芯片的焊盘被连接到引线指。 将密封剂分配到引线框架的第二侧上并且覆盖引线指及其电连接。 将凝胶分配到模具的顶表面上并覆盖芯片接合焊盘及其电连接。 盖子连接到引线框架并覆盖模具和凝胶，并且盖的侧面穿透密封剂。

公开(公告)号：US20120306031A1

公开(公告)日：2012-12-06

申请号：US13118596

申请日：2011-05-31

申请人： Wai Yew Lo ,  Lan Chu Tan

发明人： Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L29/84 ,  H01L21/54

CPC分类号： H01L21/561 ,  G01L19/0627 ,  G01L19/143 ,  G01L19/147 ,  H01L21/568 ,  H01L23/04 ,  H01L23/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/85013 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor sensor die is packaged with a footed lid that has side walls and a top portion with a central hole. Gel material is dispensed into a cavity formed by the side walls such that it covers the die prior to attaching the lid top portion.

摘要翻译： 半导体传感器芯片包括具有侧壁的底盖和具有中心孔的顶部部分。 将凝胶材料分配到由侧壁形成的空腔中，使得其在附接盖顶部分之前覆盖模具。

公开(公告)号：US07042098B2

公开(公告)日：2006-05-09

申请号：US10613703

申请日：2003-07-07

申请人： Fuaida Harun ,  Liang Jen Koh ,  Lan Chu Tan

发明人： Fuaida Harun ,  Liang Jen Koh ,  Lan Chu Tan

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. Vias in the package substrate provide electrical connection between the top and bottom sides. The vias have a via capture pad to which a wire may be wire bonded so that the wires from the IC to the substrate top side directly contact the vias at their capture pads without the need for traces from a top side bond pad to a via. The via capture pad is shaped to include at least one sharp edge to improve the ability of a wirebonder with pattern recognition software to locate the capture pad and place the wire.

摘要翻译： 使用封装基板封装集成电路，该封装基板的底侧具有规则的连接点阵列，顶部具有集成电路。 封装衬底中的通孔提供顶部和底部之间的电连接。 通孔具有通孔捕获垫，导线可以被引线接合到该通孔捕获垫，使得从IC到基板顶侧的导线直接接触它们的捕获垫处的通孔，而不需要从顶侧接合焊盘到通孔的迹线。 通孔捕获垫被成形为包括至少一个锋利边缘，以提高带有图案识别软件的引线键合器定位捕获垫并放置导线的能力。

公开(公告)号：US09202770B1

公开(公告)日：2015-12-01

申请号：US14474291

申请日：2014-09-01

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L23/367 ,  H01L21/56 ,  B29B9/12

CPC分类号： H01L23/3675 ,  B29B9/12 ,  B29C45/02 ,  B29C45/14655 ,  B29C45/1634 ,  B29C45/1671 ,  B29C45/462 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A packaged semiconductor device has an integrated circuit (IC) die and first and second volumes of molding compound. The first volume of molding compound is disposed on a first portion of a first side of the IC die and comprises a first molding compound. The second volume of molding compound is disposed on a second side of the IC die, different from the first side, and comprises a second molding compound, different from the first molding compound. By including different molding compounds, the properties of the packaged semiconductor device can be varied across the device.

摘要翻译： 封装的半导体器件具有集成电路（IC）模具和第一和第二体积的模塑料。 第一体积的模塑料被设置在IC模头的第一侧的第一部分上并且包括第一模塑料。 第二体积的成型化合物设置在IC模具的与第一侧不同的第二侧上，并且包括与第一模塑料不同的第二模塑料。 通过包括不同的成型化合物，封装的半导体器件的性能可以在整个器件上变化。

公开(公告)号：US20150201489A1

公开(公告)日：2015-07-16

申请号：US14151828

申请日：2014-01-10

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11

CPC分类号： H05K3/007 ,  H05K1/097 ,  H05K2203/107

摘要： A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

摘要翻译： 电路互连衬底制造方法包括在载体的顶部上沉积第一层金属粉末，然后从第一层金属粉末形成第一层导电迹线。 然后将第二层金属粉末沉积到第一层导电迹线的至少一个区域上。 然后从第二层金属粉末形成第二层导电迹线，并且第二层的每个迹线电耦合到第一层的迹线。 将绝缘材料沉积到载体上以提供支撑迹线的绝缘基板。 该方法不需要使用任何湿化学品或化学蚀刻步骤。

公开(公告)号：US20150137354A1

公开(公告)日：2015-05-21

申请号：US14086932

申请日：2013-11-21

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03442 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/03552 ,  H01L2224/0381 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11505 ,  H01L2224/11552 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/136 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2224/11442 ,  H01L2924/014 ,  H01L2924/00

摘要： A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.

摘要翻译： 通过在芯片的表面上的导电焊盘上施加金属粉末，在集成电路芯片上形成诸如铜柱凸起的柱状凸块。 选择性地点燃金属粉末以形成柱状凸块。 任何剩余的非固化金属粉末可以从芯片的表面去除。 可以重复该过程以增加凸起高度。 此外，可以在柱状凸起的外表面上形成焊锡帽。