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1.
公开(公告)号:US06658762B2
公开(公告)日:2003-12-09
申请号:US10124481
申请日:2002-04-18
申请人: Yih Chang , Jung-Lung Liu , Chih-Jen Yang , Chih-Ming Kuo , Jih-Yi Wang , Tien-Rong Lu
发明人: Yih Chang , Jung-Lung Liu , Chih-Jen Yang , Chih-Ming Kuo , Jih-Yi Wang , Tien-Rong Lu
IPC分类号: F26B504
CPC分类号: H01L21/67775 , H01L51/0001 , H01L51/5012 , Y10S414/139
摘要: A method and an apparatus for transporting substrates in all organic light emitting diode (OLED) process is disclosed, which has a transferring chamber provided for transporting substrates between processing modules and the atmosphere condition therein is able to be adjusted to be the same as the processing module by an atmosphere conditioner unit. According to the present invention, the substrates are not contaminated by moisture and the process operation and the factory layout are more flexible. Moreover, the OLED yield is improved.
摘要翻译: 公开了一种用于在所有有机发光二极管(OLED)工艺中传输衬底的方法和装置,其具有设置用于在处理模块之间传送衬底的传送室,并且其中的气氛条件能够被调整为与处理相同 模块由大气调节装置组成。 根据本发明,基板不被水分污染,并且工艺操作和工厂布局更灵活。 此外,OLED产率提高。
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2.
公开(公告)号:US06393716B1
公开(公告)日:2002-05-28
申请号:US09563932
申请日:2000-05-04
申请人: Yih Chang , Jung-Lung Liu , Chih-Jen Yang , Chih-Ming Kuo , Jih-Yi Wang , Tien-Rong Lu
发明人: Yih Chang , Jung-Lung Liu , Chih-Jen Yang , Chih-Ming Kuo , Jih-Yi Wang , Tien-Rong Lu
IPC分类号: B65G4907
CPC分类号: H01L21/67775 , H01L51/0001 , H01L51/5012 , Y10S414/139
摘要: A method and an apparatus for transporting substrates in an organic light emitting diode (OLED) process is disclosed, which has a transferring chamber provided for transporting substrates between processing modules and the atmosphere condition therein is able to be adjusted to be the same as the processing module by an atmosphere conditioner unit. According to the present invention, the substrates are not contaminated by moisture and the process operation and the factory layout are more flexible. Moreover, the OLED yield is improved.
摘要翻译: 公开了一种用于在有机发光二极管(OLED)工艺中传输衬底的方法和装置,其具有设置用于在处理模块之间传送衬底的传送室,并且其中的气氛条件能够被调整为与处理相同 模块由大气调节装置组成。 根据本发明,基板不被水分污染,并且工艺操作和工厂布局更灵活。 此外,OLED产率提高。
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公开(公告)号:US06963214B2
公开(公告)日:2005-11-08
申请号:US10822524
申请日:2004-04-12
申请人: Shun-Chi Huang , Chih-Ming Kuo
发明人: Shun-Chi Huang , Chih-Ming Kuo
CPC分类号: G01R31/2841
摘要: Methods and apparatus for testing a semiconductor structure requiring a precise core or operating voltage with an OBIRCH analysis arrangement. The separate power supply used for providing the precise core or operating voltage is eliminated, and is replaced by connecting a circuit comprised of a plurality of Schottky diodes connected in series across the constant voltage power supply used to provide the current for the OBIRCH analysis. A precise voltage is then tapped from an anode of the series connected Schottky diodes thereby significantly reducing effects of background noise on the OBIRCH analysis.
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公开(公告)号:US08953309B2
公开(公告)日:2015-02-10
申请号:US13616677
申请日:2012-09-14
申请人: Cheng-Mao Chang , Ching-Piao Kuan , Chih-Ming Kuo , Yan-Lin Kuo
发明人: Cheng-Mao Chang , Ching-Piao Kuan , Chih-Ming Kuo , Yan-Lin Kuo
IPC分类号: H05K5/00
摘要: An electronic device is provided, including a main body, a bottom shell, and an electrical connection port. The bottom shell is pivotally connected to the main body, and the electrical connection port is disposed on the bottom shell. When the bottom shell is in a closed position relative to the main body, the electrical connection port is covered by the main body. When the bottom shell rotates from the closed position to an opened position relative to the main body, an opening is formed between the main body and the bottom shell, and the electrical connection port is exposed to the opening.
摘要翻译: 提供一种电子设备,包括主体,底壳和电连接端口。 底壳枢转地连接到主体,并且电连接端口设置在底壳上。 当底壳相对于主体处于关闭位置时,电连接口被主体覆盖。 当底壳从关闭位置相对于主体旋转到打开位置时,在主体和底壳之间形成开口,并且电连接口暴露于开口。
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公开(公告)号:US08692390B2
公开(公告)日:2014-04-08
申请号:US13030203
申请日:2011-02-18
申请人: Chih-Hung Wu , Lung-Hua Ho , Chih-Ming Kuo , Cheng-Hung Shih , Yie-Chuan Chiu
发明人: Chih-Hung Wu , Lung-Hua Ho , Chih-Ming Kuo , Cheng-Hung Shih , Yie-Chuan Chiu
IPC分类号: H01L29/40
CPC分类号: H01L23/49811 , H01L23/295 , H01L2224/10126 , H01L2224/13565 , H01L2224/81191 , H01L2224/83192 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要: A pyramid bump structure for electrically coupling to a bond pad on a carrier comprises a conductive block disposed at the bond pad and an oblique pyramid insulation layer covered at one side of the conductive block. The oblique pyramid insulation layer comprises a bottom portion and a top portion, and outer diameter of the oblique pyramid insulation layer is tapered from the bottom portion to the top portion. When the carrier is connected with a substrate and an anisotropic conductive film disposed at the substrate, the pyramid bump structure may rapidly embed into the anisotropic conductive film to raise the flow rate of the anisotropic conductive film. Further, a short phenomenon between adjacent bumps can be avoided to raise the yield rate of package process.
摘要翻译: 用于电耦合到载体上的接合焊盘的金字塔凸块结构包括设置在接合焊盘处的导电块和在导电块的一侧被覆盖的斜锥形绝缘层。 倾斜金字塔绝缘层包括底部和顶部,倾斜金字塔绝缘层的外径从底部到顶部逐渐变细。 当载体与衬底连接并且设置在衬底上的各向异性导电膜时,金字塔凸块结构可以快速地嵌入到各向异性导电膜中以提高各向异性导电膜的流速。 此外,可以避免相邻凸点之间的短暂现象,以提高封装处理的成品率。
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公开(公告)号:US08658466B2
公开(公告)日:2014-02-25
申请号:US13525460
申请日:2012-06-18
申请人: Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
发明人: Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
IPC分类号: H01L21/00
CPC分类号: H01L23/49811 , H01L21/4846 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1147 , H01L2224/11472 , H01L2224/11831 , H01L2224/11903 , H01L2224/11906 , H01L2224/13011 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/8114 , H01L2224/81193 , H01L2224/81345 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/014
摘要: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
摘要翻译: 半导体封装结构包括第一衬底,第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上,并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。
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公开(公告)号:US08581384B2
公开(公告)日:2013-11-12
申请号:US13426804
申请日:2012-03-22
申请人: Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Lung-Hua Ho , Chih-Hsien Ni
发明人: Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Lung-Hua Ho , Chih-Hsien Ni
IPC分类号: H01L23/48
CPC分类号: H01L23/49548 , H01L23/3107 , H01L23/49582 , H01L23/49586 , H01L2224/16245
摘要: A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.
摘要翻译: 半导体封装结构包括引线框架,至少一个芯片,模塑料和抗导电膜。 引线框架包括多个引线,每个引线包括第一端部和第二端部,其中第一端部包括第一上表面和第一下表面,并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。
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公开(公告)号:US08415243B1
公开(公告)日:2013-04-09
申请号:US13352530
申请日:2012-01-18
申请人: Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
发明人: Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
IPC分类号: H01L21/44
CPC分类号: H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/0347 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/11472 , H01L2224/1182 , H01L2224/11906 , H01L2224/13147 , H01L2224/13562 , H01L2224/13564 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2924/01074 , H01L2924/01079 , H01L2924/01029 , H01L2924/01028 , H01L2224/05552
摘要: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.
摘要翻译: 凸起工艺包括提供硅衬底,在硅衬底上形成含钛金属层,其中含钛金属层包括多个第一区域和多个第二区域,在含钛金属层上形成光致抗蚀剂层 金属层,图案化光致抗蚀剂层以形成多个开口槽,在开口槽处形成多个底部覆盖层,进行热过程,形成多个外部覆盖层,以使每个外部覆盖层与每个 的底部覆盖层,其中所述外部覆盖层和所述底部覆盖层形成包裹层并且完全围绕铜凸块,在外部覆盖层上形成多个连接层,去除光致抗蚀剂层,去除第二区域并使能 每个第一区域形成凸块下的冶金层。
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9.
公开(公告)号:US6117282A
公开(公告)日:2000-09-12
申请号:US935739
申请日:1997-09-23
申请人: Po-Cheng Kuo , Chih-Ming Kuo
发明人: Po-Cheng Kuo , Chih-Ming Kuo
CPC分类号: C23C14/5806 , C23C14/0652 , C23C14/185 , G11B5/656 , G11B5/84 , G11B5/851 , H01F10/132
摘要: A method of producing SiNx protected amorphous Co-Tb thin films with high coercivity for longitudinal and perpendicular magnetic recording media is described. The method includes magnetron sputtering at controlled sputtering power and sputtering argon gas pressure to form a selective composition of amorphous Co-Tb thin film on a low temperature substrate. After the Co-Tb film is deposited, a protective SiNx layer with thickness of 100 .ANG. was produced on the film. The as-deposited film has an amorphous structure with a high value of coercivity, and its magnetic easy-axis is perpendicular to the film plane. This film can be used as a perpendicular magnetic recording medium. After low temperature annealing at controlled conditions for a desirable temperature and time period in vacuum, the film also has an amorphous structure but its magnetic properties are isotropic. This film can be used as a longitudinal magnetic recording medium.
摘要翻译: 描述了制造用于纵向和垂直磁记录介质的具有高矫顽力的SiNx保护的无定形Co-Tb薄膜的方法。 该方法包括在受控溅射功率和溅射氩气压力下的磁控溅射,以在低温基底上形成非晶Co-Tb薄膜的选择性组成。 在沉积Co-Tb膜之后,在膜上产生厚度为100安培的保护性SiNx层。 沉积膜具有矫顽磁力高的非晶结构,其磁性容易轴垂直于膜平面。 该膜可以用作垂直磁记录介质。 在控制条件下在真空中达到所需温度和时间段的低温退火后,该膜也具有非晶结构,但其磁特性是各向同性的。 该膜可以用作纵向磁记录介质。
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公开(公告)号:US20130193570A1
公开(公告)日:2013-08-01
申请号:US13363479
申请日:2012-02-01
申请人: Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
发明人: Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
IPC分类号: H01L23/498 , H01L21/768
CPC分类号: H01L21/76885 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05184 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/11472 , H01L2224/11903 , H01L2224/13147 , H01L2224/13562 , H01L2224/13564 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2224/05552
摘要: A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.
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