公开(公告)号：EP2993692A2

公开(公告)日：2016-03-09

申请号：EP15170728.8

申请日：2015-06-04

申请人： Samsung Electronics Co., Ltd

发明人： Chu, Kunmo ,  Moon, Changyoul ,  Lee, Sunghee ,  Hwang, Junsik

IPC分类号： H01L21/58 ,  H01L23/14 ,  H01L33/48 ,  H01S5/022 ,  H01L25/065 ,  H01L21/98

CPC分类号： H01L25/50 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L33/0079 ,  H01L2224/04026 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/24146 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32503 ,  H01L2224/33181 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2933/0066 ,  H01L2224/83 ,  H01L2924/014 ,  H01L21/78 ,  H01L2224/81 ,  H01L2224/45099

摘要： The present disclosure provides semiconductor chips (SC10, SC11), semiconductor devices and methods of manufacturing the semiconductor devices. The semiconductor device includes a base substrate (S100) and a semiconductor chip (SC10, SC11) on the base substrate (S100), the semiconductor chip (SC10, SC11) including a first layer structure (L10) and a second layer structure (L20) opposite to the first layer structure (L10), at least one of the first and second layer structures (L10, L20) including a semiconductor device portion, and a bonding structure (B10, B11) between the first layer structure (L10) and the second layer structure (L20), the bonding structure (B10, B11) including a silver-tin compound (Ag3Sn) and a nickel-tin compound (Ni3Sn4 and optionally also Ni3Sn). The semiconductor portion may be a light-emitting device portion, wherein the first layer structure (L10) includes a silicon substrate and the second layer structure (L20) includes the light-emitting device portion, which includes a group III-V semiconductor, for example, a GaN-based semiconductor. The method of manufacturing a semiconductor device comprises forming a first metal layer on a first substrate structure, the first metal layer including a first nickel (Ni) layer and a first tin (Sn) layer; forming a second metal layer on a second substrate structure, the second metal layer including a second Ni layer and optionally a second Sn layer on the second Ni layer; forming a capping layer between the first and second metal layers, the capping layer including silver (Ag); and forming a bonding structure including bonding the first metal layer formed on the first substrate structure to the second metal layer formed on the second substrate structure, and forming an intermediate layer between the first metal layer and the second metal layer by a reaction between the first and second metal layers and the capping layer, the intermediate layer including intermetallic compounds (Ag3Sn, Ni3Sn4 and optionally Ni3Sn). The Ag3Sn that is formed by a reaction between Ag and Sn fills a void region which occurs due to a volume contraction of a bonding portion occurring during a reaction between Ni and Sn.

摘要翻译： 本发明提供的半导体芯片（SC10，SC11），半导体器件和制造半导体器件的方法。 该半导体器件包括在基础基板的基座基板（S100）和半导体芯片（SC10，SC11）（S100），半导体芯片（SC10，SC11）包括第一层结构（L10）和第二层结构（L20 ）相反的第一层结构（L10），所述第一和第二层结构（L10，L20），包括第一层结构（L10之间的半导体器件部分，和一个接合结构（B10，B11）中的至少一个），并 包括银 - 锡化合物（AG 3 Sn）和镍 - 锡化合物（Ni3Sn4金属并因此OPTIONALLY的Ni 3 Sn）的第二层结构（L20），所述接合结构（B10，B11）。 半导体部分可以是一个发光器件部分，worin第一层结构（L10）包括硅衬底和所述第二层结构（L20）的步骤包括在发光器件部分，其包括III-V族半导体， 例如，基于GaN的半导体。 制造半导体器件的方法包括：形成在第一基板的结构的第一金属层，第一金属层包括第一镍（Ni）层和第一锡（Sn）层; 上形成第二基板结构的第二金属层，第二金属层包括第二Ni层和第二Ni层上的第二OPTIONALLY Sn层; 形成第一和第二金属层之间的覆盖层，覆盖层包括银（Ag）; 以及形成的接合结构，包括形成在所述第一基板结构，以形成在所述第二基板结构中的第二金属层的第一金属层接合，并通过第一之间的反应在所述第一金属层和第二金属层之间的中间层形成 和第二金属层和覆盖层，所述中间层包括金属间化合物（AG 3锡，镍3 Sn的Ni3Sn4金属和任选的）。 银3的Sn没有被被Ag和Sn之间的反应形成填充哪个发生空隙区域由于接合部的Ni和Sn之间的反应过程中发生的体积收缩。

公开(公告)号：EP2858107A3

公开(公告)日：2015-10-21

申请号：EP14176759.0

申请日：2014-07-11

申请人： Kabushiki Kaisha Toshiba

发明人： Matsushita, Keiichi ,  Sasaki, Yo

IPC分类号： H01L23/373 ,  H01L21/58 ,  H01L23/10 ,  H01L21/50

CPC分类号： H01L23/3736 ,  H01L21/50 ,  H01L23/10 ,  H01L23/142 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05647 ,  H01L2224/2741 ,  H01L2224/2743 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83359 ,  H01L2224/83379 ,  H01L2224/83447 ,  H01L2224/83825 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/161 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/171 ,  H01L2924/2064 ,  H01L2224/05644 ,  H01L2924/00012 ,  H01L2224/06164 ,  H01L2224/45099

摘要： According to one embodiment, a semiconductor device (110) includes a semiconductor element (20), a mounting member (70) including Cu, and a bonding layer (50) provided between the semiconductor element (20) and the mounting member (70). The bonding layer (50) includes a first region (R1) including Ti and Cu, and a second region (R2) provided between the first region (R1) and the mounting member (70), and including Sn and Cu. A first position (P1) along the first direction is positioned between the semiconductor element (20) and a second position (P2) along the first direction. The first position (P1) is where the composition ratio (51r) of Ti in the first region (R1) is 0.1 times a maximum value (51x) of the composition ratio (51r) of Ti. The second position (P2) is where the composition ratio (52r) of Sn in the second region (R2) is 0.1 times a maximum value (52x) of the composition ratio (52r) of Sn. A distance (L1) between the first position (P1) and the second position (P2) is not less than 0.1 micrometres.
According to another embodiment, a semiconductor device (120) includes a semiconductor element (20), a mounting member (70) including Cu, a first layer (41) provided between the semiconductor element (20) and the mounting member (70), the first layer (41) including Ti, a second layer (42) provided between the first layer (41) and the mounting member (70), the second layer (42) including Sn and Cu and a third layer (43) provided between the first layer (41) and the second layer (42), the third layer (43) including at least one selected from Ni, Pt, and Pd.
In both embodiments, the semiconductor device (110, 120) is formed by bonding the semiconductor element (20) to the mounting member (70) by solid solution bonding.
Thereby, a semiconductor device (110, 120) having good heat dissipation and high productivity can be provided.

公开(公告)号：EP2920810A2

公开(公告)日：2015-09-23

申请号：EP13811692.6

申请日：2013-12-02

申请人： Invensas Corporation

发明人： UZOH, Cyprian, Emeka

IPC分类号： H01L23/485 ,  H01L23/498 ,  H01L21/60 ,  H05K3/34 ,  H01L23/10 ,  H01L21/50

CPC分类号： H05K13/046 ,  H01L21/4853 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H01L2224/02372 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05138 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1319 ,  H01L2224/14131 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81075 ,  H01L2224/8112 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/83075 ,  H01L2224/8312 ,  H01L2224/83193 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2924/381 ,  H01L2924/04953 ,  H01L2924/01071 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01031 ,  H01L2924/01034 ,  H01L2924/00012 ,  H01L2924/07025 ,  H01L2224/05552

摘要： A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

公开(公告)号：EP1657739A3

公开(公告)日：2012-12-19

申请号：EP05110381.0

申请日：2005-11-04

申请人： Oki Data Corporation

发明人： Ogihara, Mitsuhiko, c/o Oki Digital Imaging Corp. ,  Fujiwara, Hiroyuki, c/o Oki Digital Imaging Corp. ,  Suzuki, Takahito, c/o Oki Digital Imaging Corp. ,  Sakuta, Masaaki ,  Abiko, Ichimatsu

IPC分类号： H01L21/60 ,  B41J2/45

CPC分类号： H01L24/83 ,  B41J2/45 ,  H01L24/29 ,  H01L24/32 ,  H01L27/153 ,  H01L2224/27444 ,  H01L2224/2747 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29114 ,  H01L2224/29117 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/32502 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/10349 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00

摘要： A semiconductor composite apparatus includes a semiconductor thin film layer (105, 501, 806) and a substrate (101, 503, 801). The semiconductor thin film layer (105, 501, 806) and the substrate are bonded to each other with a layer of an alloy (121+122, 511+512, 911+912) of a high-melting-point metal and a low-melting-point metal formed between the semiconductor thin film layer and the substrate. The alloy has a higher melting point than the low-melting-point metal (104, 404, 804). The layer of the alloy (121+122, 511+512, 911+912) contains a product (122, 511, 912) resulting from a reaction of the low-melting-point metal (104, 404, 804) and a material of said semiconductor thin film layer (105, 501, 806).

公开(公告)号：EP2521174A2

公开(公告)日：2012-11-07

申请号：EP12178601.6

申请日：2006-03-17

申请人： DOWA Electronics Materials Co., Ltd.

发明人： Oshika, Yoshikazu ,  Nakano, Masayuki

IPC分类号： H01L23/498

CPC分类号： H05K1/111 ,  B23K35/001 ,  H01L21/4864 ,  H01L23/15 ,  H01L23/49811 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/83 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/14 ,  H01L2924/15724 ,  H01L2924/351 ,  H05K1/0306 ,  H05K3/341 ,  H05K3/388 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2224/48

摘要： A submount (50) comprising a submount substrate (52) and a solder layer (54) adherently deposited on the submount substrate (52) for soldering with a semiconductor device, characterized in that said solder layer (54) is formed of constituent elements in a composition ratio which varies in a depth direction of said solder layer (54).

摘要翻译： 一种底座（50），包括一个副安装座基板（52）和一个焊接层（54），该焊接层粘贴在该副安装座基板（52）上用于与半导体器件焊接，其特征在于，所述焊料层（54）由 在所述焊料层（54）的深度方向上变化的组成比。

公开(公告)号：EP2398046A1

公开(公告)日：2011-12-21

申请号：EP10166436.5

申请日：2010-06-18

申请人： NXP B.V.

发明人： Rother, Michael

IPC分类号： H01L21/60 ,  H01L23/482

CPC分类号： H01L24/29 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/31 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/85411 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15747 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2924/00014

摘要： Circuit components (110,160) are joined using a copper-tin (Cu-Sn) alloy. A barrier layer/adhesion promoter (120) is sputtered on a bond connection surface (112) of a package component (110), a seed layer of copper (130) is applied thereon and a copper layer (140) is plated on the seed layer (130). The copper layer (140) is put in contact with a tin layer (150) by positioning a package component (160), having a layer of tin (150) thereon. The copper and tin layers (140,150) are heated to form a Cu-Sn alloy, melt the Cu-Sn alloy and react substantially all of the tin to form a Cu-Sn intermetallic compound (170) from the alloy, physically and electrically coupling components (110,160) together. Component (110) may be a semiconductor or integrated circuit substrate. Component (160) may be a leadframe or a circuit board. The barrier layer/adhesion promoter (120), the Cu seed layer (130) and the plated Cu layer (140) may be patterned. The tin layer (140) may alternatively be formed directly on the plated Cu layer (130).

摘要翻译： 电路部件（110.160）使用的是铜 - 锡（Cu-Sn金属）合金接合。 阻挡层/粘附促进剂（120）上的封装元件（110），铜的籽晶层的键合连接表面（112）溅射（130）在其上应用和铜层（140）镀到种子上 层（130）。 铜层（140）被放置在用锡层（150）由定位具有（150）在其上锡的层的封装部件（160）接触。 在铜和锡的层（140,150）加热以形成Cu-Sn合金，熔融的Cu-Sn合金和反应基本上所有的锡以形成从合金的Cu-Sn的金属间化合物（170），物理和电耦合 组分（110.160）在一起。 部件（110）可以是半导体或集成电路的衬底。 部件（160）可以是引线框或电路板上。 在阻挡层/粘附促进剂（120），所述Cu籽晶层（130）和镀Cu层（140）可被图案化。 锡层（140）可以可选地在镀Cu层（130）上直接形成。

公开(公告)号：EP2328192A2

公开(公告)日：2011-06-01

申请号：EP10172857.4

申请日：2010-08-16

申请人： Industrial Technology Research Institute

发明人： Lin, Hsiu-Jen ,  Lin, Jian-Shian ,  Chen, Shau-Yi ,  Lai, Chieh-Lung

IPC分类号： H01L33/62 ,  H01L33/00

CPC分类号： H01L23/53247 ,  H01L24/29 ,  H01L24/83 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/30 ,  H01L33/40 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/83193 ,  H01L2224/83207 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/00014

摘要： A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110°C, and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200°C.

摘要翻译： 芯片接合方法适合于将具有第一金属薄膜层的LED芯片芯片接合到基板上。 该方法包括在基板的表面上形成第二金属薄膜层; 在所述第二金属薄膜层上形成芯片接合材料层; 将第一金属薄膜层与芯片接合材料层接触，将LED芯片放置在芯片接合材料层上; 在液固固体反应温度下加热芯片接合材料层以进行预固化时间，以形成第一金属间层和第二金属间层; 并在固 - 固反应温度下加热芯片接合材料层达固化时间，以进行固 - 固反应。 液固反应温度和固 - 固反应温度都低于110℃，固 - 固反应后第一和第二金属间化合物的熔点高于200℃。

公开(公告)号：EP1748480A1

公开(公告)日：2007-01-31

申请号：EP05016387.2

申请日：2005-07-28

申请人： Infineon Technologies AG

发明人： Otremba, Ralf, Dipl.-Phys./Dipl.-Ing. (FH)

IPC分类号： H01L21/60 ,  H01L23/495

CPC分类号： H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32507 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Connection structure (5) for attaching a semiconductor chip (2) to a metal substrate (4) is provided which comprises a plurality of electrically conducting layers (11,12,13,14) arranged in a stack. The stack comprises a contact layer (11) for providing an ohmic contact to a semiconductor chip (2), at least one mechanical decoupling layer (12) for mechanically decoupling the semiconductor chip (2) and the metal substrate (4), at least one diffusion barrier layer (13) and a diffusion solder layer (14) for providing a diffusion soldered mechanical bond and an electrical connection to a metal substrate (4). The mechanical decoupling layer (12) is positioned in the stack between the diffusion barrier layer (13) and the contact layer (11) and serves to relieve stress and reduce crack formation during thermal cycling due to differences in thermal expansion coefficients.

摘要翻译： 提供了一种用于半导体芯片（2）附接至金属基体（4）的连接结构（5），其包括以堆叠布置的导电层（11,12,13,14）的复数。 堆叠在欧姆接触，用于机械地提供到半导体芯片（2），至少一个机械解耦层（12）去耦的半导体芯片（2）和所述金属基体（4），至少包括一个接触层（11） 一个扩散阻挡层（13）和用于提供扩散扩散焊料层（14）焊接的机械键和上金属基板（4）的电连接。 机械解耦层（12）在所述扩散阻挡层（13）和接触层（11）之间的堆定位，并且用于减轻压力，减少热循环过程中的裂纹形成由于热膨胀系数的不同。

公开(公告)号：EP1720204A1

公开(公告)日：2006-11-08

申请号：EP06112160.4

申请日：2006-04-03

申请人： ROSEMOUNT AEROSPACE INC.

发明人： Eriksen, Odd Harald Steen ,  Guo, Shuwen ,  Childress, Kimiko

IPC分类号： H01L21/762

CPC分类号： H01L24/83 ,  H01L21/7624 ,  H01L24/26 ,  H01L2224/83141 ,  H01L2224/83805 ,  H01L2224/83825 ,  H01L2224/8385 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1461 ,  Y10T428/13 ,  Y10T428/31678 ,  H01L2924/00 ,  H01L2224/83205

摘要： A method for bonding two components together including the steps of providing a first component, providing a second component, and locating a first eutectic bonding material between the first and second component. The first eutectic bonding material includes at least one of germanium, tin, or silicon. The method further includes the step of locating a second eutectic bonding material between the first and second component and adjacent to the first eutectic bonding material. The second eutectic bonding material includes gold. The method further includes the step of heating the first and second eutectic bonding materials to a temperature above a eutectic temperature of an alloy of the first and second eutectic bonding materials to allow a hypoeutectic alloy to form out of the first and second eutectic bonding materials. The method includes the further step of cooling the hypoeutectic alloy to form a solid solution alloy bonding the first and second components together.

摘要翻译： 一种用于将两个部件结合在一起的方法，包括提供第一部件，提供第二部件以及在第一和第二部件之间定位第一共晶接合材料的步骤。 第一共晶接合材料包括锗，锡或硅中的至少一种。 该方法还包括在第一和第二部件之间并与第一共晶接合材料相邻定位第二共晶接合材料的步骤。 第二共晶接合材料包括金。 该方法还包括将第一和第二共晶接合材料加热到高于第一和第二共晶接合材料的合金的共晶温度的温度以允许亚共晶合金从第一和第二共晶接合材料形成的步骤。 该方法包括进一步冷却亚共晶合金以形成将第一和第二组分结合在一起的固溶体合金。

公开(公告)号：EP1657739A2

公开(公告)日：2006-05-17

申请号：EP05110381.0

申请日：2005-11-04

申请人： Oki Data Corporation

发明人： Ogihara, Mitsuhiko, c/o Oki Digital Imaging Corp. ,  Fujiwara, Hiroyuki, c/o Oki Digital Imaging Corp. ,  Suzuki, Takahito, c/o Oki Digital Imaging Corp. ,  Sakuta, Masaaki ,  Abiko, Ichimatsu

IPC分类号： H01L21/20

CPC分类号： H01L24/83 ,  B41J2/45 ,  H01L24/29 ,  H01L24/32 ,  H01L27/153 ,  H01L2224/27444 ,  H01L2224/2747 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29114 ,  H01L2224/29117 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/32502 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/10349 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00

摘要： A semiconductor composite apparatus includes a semiconductor thin film layer (105, 501, 806) and a substrate (101, 503, 801). The semiconductor thin film layer (105, 501, 806) and the substrate are bonded to each other with a layer of an alloy (121+122, 511+512, 911+912) of a high-melting-point metal and a low-melting-point metal formed between the semiconductor thin film layer and the substrate. The alloy has a higher melting point than the low-melting-point metal (104, 404, 804). The layer of the alloy (121+122, 511+512, 911+912) contains a product (122, 511, 912) resulting from a reaction of the low-melting-point metal (104, 404, 804) and a material of said semiconductor thin film layer (105, 501, 806).

摘要翻译： 一种半导体复合装置包括半导体薄膜层（105，501，806）和衬底（101，503，801）。 半导体薄膜层（105，501，806）和所述衬底键合到彼此的合金的层（121 + 122，511 + 512，911 + 912）的高熔点金属和低的 半导体薄膜层和基片之间-melting点金属构成。 该合金具有比低熔点金属（104，404，804）具有更高的熔点。 该合金的层（121 + 122，511 + 512，911 + 912）包含一个产品（122，511，912）从低熔点金属（104，404，804）和一个材料的反应得到的 所述半导体薄膜层（105，501，806）的。