公开(公告)号：US09798088B2

公开(公告)日：2017-10-24

申请号：US14933668

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Robert K. Leidy ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Eric Turcotte ,  Thomas E. Lombardi

IPC: G02B6/30 ,  G02B6/13

CPC classification number: G02B6/30 ,  G02B6/13 ,  G02B6/4239 ,  G02B6/4243 ,  G02B6/428

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

公开(公告)号：US09585257B2

公开(公告)日：2017-02-28

申请号：US14668031

申请日：2015-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  David J. Russell

IPC: H05K3/02 ,  H05K3/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/373 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H01L21/60

CPC classification number: H05K3/0094 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76877 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2021/60007 ,  H01L2224/16225 ,  H05K1/0201 ,  H05K1/115 ,  H05K3/4038

Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias in addition to electrically conductive vias. The thermally conductive vias help dissipate heat from one or more IC chips, through the glass interposer, into an organic carrying, and then, into an underlying substrate where it can be dissipated.

Abstract translation: 本发明一般涉及集成电路（IC）芯片封装，更具体地，涉及一种形成具有导电通孔的玻璃插入件以及导电通孔的结构和方法。 导热通孔有助于从一个或多个IC芯片（通过玻璃插入件）将热量散发到有机载体中，然后进入可以被耗散的底层基板。

公开(公告)号：US09425269B1

公开(公告)日：2016-08-23

申请号：US14747604

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41708 ,  H01L21/76804 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating such device structures. An emitter structure is formed that has a semiconductor layer with a top surface defining a recess and a sacrificial layer comprised of a disposable material in the recess. A contact opening is formed that extends through one or more first dielectric layers to the sacrificial layer. After the contact opening is formed, the sacrificial layer is removed from the recess. Alternatively, the layer in the recess may be comprised of a non-disposable material that may occupy the recess at the time that a contact is formed in the contact opening.

Abstract translation: 双极结型晶体管的器件结构及其制造方法。 形成发射体结构，其具有半导体层，其具有限定凹部的顶表面和在凹部中由一次性材料构成的牺牲层。 形成了延伸穿过一个或多个第一介电层到牺牲层的接触开口。 在形成接触开口之后，从凹部移除牺牲层。 或者，凹部中的层可以由在接触开口中形成接触时可能占据凹部的非一次性材料构成。

公开(公告)号：US09397054B2

公开(公告)日：2016-07-19

申请号：US14876889

申请日：2015-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/58 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03

Abstract: A semiconductor structure with an interconnect level above a substrate and including a conductive pad and a metallic structure, such as a base of a crackstop. A first dielectric layer is above the conductive pad and above the metallic structure. A first opening in the first dielectric layer is aligned with and exposes the conductive pad and a second opening is aligned with and exposes the metallic structure. A metallic liner lines the first opening and the second opening and is on the top surface of the first dielectric layer. A second dielectric layer is above the metallic liner and a third dielectric layer is above the second dielectric layer. A third opening exposes a portion of the metal liner above the conductive pad and a copper plug and pedestal are in the third opening on the exposed portion of the metal liner.

Abstract translation: 一种半导体结构，其具有在衬底上方的互连水平并且包括导电焊盘和金属结构，例如裂缝挡板的基部。 第一介电层位于导电焊盘的上方，并在金属结构之上。 第一介电层中的第一开口与导电焊盘对准并且暴露，并且第二开口与金属结构对准并且暴露出金属结构。 金属衬垫将第一开口和第二开口线排列在第一介电层的顶表面上。 第二电介质层在金属衬垫之上，第三电介质层位于第二电介质层之上。 第三个开口将金属衬垫的一部分暴露在导电垫的上方，铜插头和基座位于金属衬垫的暴露部分的第三个开口中。

公开(公告)号：US09257352B2

公开(公告)日：2016-02-09

申请号：US13835358

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: G01R31/02 ,  G01R31/26 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer.

Abstract translation: 公开了一种测试晶片，其第一侧被配置为具有形成在其上的集成电路，以及形成有测试结构的第二侧。 测试晶片可以包括嵌入晶片第二侧的电测试结构。 测试晶片的电气测试可以在通过晶片制造过程中使用的工具处理之后进行，以确定工具是否在晶片的第二侧引起缺陷。 测试结构可以包括布置在晶片的第二侧上的覆盖层。 然后可以将测试晶片暴露于湿蚀刻，然后检查是否存在由蚀刻化学物质引起的入口路径。 进入路径的存在表示在湿蚀刻之前使用的工具导致晶片中的缺陷。

公开(公告)号：US10078183B2

公开(公告)日：2018-09-18

申请号：US14966781

申请日：2015-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Prakash Periasamy ,  Donald R. Letourneau

IPC: G02B6/13 ,  G02B6/12 ,  G02B6/30 ,  G02B6/136 ,  G02B6/122

CPC classification number: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/4243 ,  G02B6/4274

Abstract: The disclosure relates to semiconductor structures and, more particularly, to waveguide structures used in phonotics chip packaging and methods of manufacture. The structure includes: a first die comprising photonics functions including a waveguide structure; a second die bonded to the first die and comprising CMOS logic functions; and an optical fiber optically coupled to the waveguide structure and positioned within a cavity formed in the second die.

公开(公告)号：US20170365775A1

公开(公告)日：2017-12-21

申请号：US15690828

申请日：2017-08-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/293 ,  H01L41/25 ,  G06F17/50 ,  H01L21/768 ,  H01L23/00 ,  H01L41/08 ,  H03H9/64 ,  H01L23/48 ,  H01L27/06 ,  H01L25/16 ,  H01L23/66 ,  H01L49/02

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

公开(公告)号：US20170131476A1

公开(公告)日：2017-05-11

申请号：US14933668

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Robert K. Leidy ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Eric Turcotte ,  Thomas E. Lombardi

IPC: G02B6/30 ,  G02B6/13

CPC classification number: G02B6/30 ,  G02B6/13 ,  G02B6/4239 ,  G02B6/4243 ,  G02B6/428

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

公开(公告)号：US09508578B2

公开(公告)日：2016-11-29

申请号：US14171874

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Max G. Levy ,  Max L. Lifson ,  Jed H. Rankin ,  Timothy D. Sullivan

IPC: H01L21/67 ,  H01L21/00 ,  G01F1/76

CPC classification number: H01L21/67288 ,  G01F1/76 ,  H01L21/00 ,  H01L21/67109

Abstract: An apparatus and method for leak detection of coolant gas from a chuck. The apparatus includes a chuck having a top surface and configured to clamp a substrate to the top surface, the chuck having one or more recessed regions in the top surface, the recessed regions configured to allow a cooling gas to contact a backside of the substrate; a cooling gas inlet and a cooling gas outlet connected to the one or more recessed regions; a first measurement device connected to the cooling gas inlet and configured to measure a first amount of cooling gas entering the cooling gas inlet and a second measurement device connected to the cooling gas outlet and configured to measure a second amount of cooling gas exiting from the cooling gas outlet; and a controller configured to determine a difference between the first amount of cooling gas and the second amount of cooling gas.

Abstract translation: 一种用于从卡盘泄漏检测冷却剂气体的装置和方法。 该装置包括具有顶表面并被配置为将基板夹持到顶表面的卡盘，卡盘在顶表面中具有一个或多个凹陷区域，凹陷区域被配置为允许冷却气体接触基板的背面; 连接到所述一个或多个凹陷区域的冷却气体入口和冷却气体出口; 连接到冷却气体入口并被配置成测量进入冷却气体入口的第一量的冷却气体的第一测量装置和连接到冷却气体出口的第二测量装置，其被配置成测量从冷却出口排出的第二量的冷却气体 气体出口; 以及控制器，被配置为确定所述第一冷却气体量与所述第二冷却气体量之间的差。

公开(公告)号：US20160043048A1

公开(公告)日：2016-02-11

申请号：US14886177

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03845 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/11011 ,  H01L2224/1134 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/2064

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.