公开(公告)号：US10304763B2

公开(公告)日：2019-05-28

申请号：US15858673

申请日：2017-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard S. Graf ,  Sudeep Mandal ,  Kibby Horsford

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

公开(公告)号：US10083891B1

公开(公告)日：2018-09-25

申请号：US15789108

申请日：2017-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Sebastian T. Ventrone ,  Ezra D. B. Hall

IPC: H01L23/38 ,  H01L27/108 ,  H01L23/34 ,  H01L25/16 ,  H01L23/498 ,  H01L23/48 ,  H01L23/367 ,  H01L35/10

CPC classification number: H01L23/38 ,  H01L23/34 ,  H01L23/345 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/16 ,  H01L27/10897 ,  H01L35/10 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311

Abstract: An IC chip package includes: a base substrate; an interposer substrate including a plurality of wires therein, the interposer substrate operatively coupled to the base substrate; and a processor operatively positioned on the interposer substrate. A memory is operatively positioned on the interposer substrate and operatively coupled to the processor through the interposer substrate. The memory includes: a 3D DRAM stack, a thermoelectric heat pump coupled directly to an uppermost layer of the 3D DRAM stack, and a memory controller operatively coupled to the 3D DRAM stack to control operation of the 3D DRAM stack. A temperature controller operatively coupled to the thermoelectric heat pump controls a temperature of the 3D DRAM stack using the thermoelectric heat pump. A lid may thermally couple to an uppermost surface of the processor and an uppermost surface of the thermoelectric heat pump.

公开(公告)号：US20170271285A1

公开(公告)日：2017-09-21

申请号：US15072655

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Kibby B. Horsford ,  Sudeep Mandal

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0332 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/0519 ,  H01L2224/0529 ,  H01L2224/05339 ,  H01L2224/05344 ,  H01L2224/05347 ,  H01L2224/05355 ,  H01L2224/0539 ,  H01L2224/05444 ,  H01L2224/05455 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01005 ,  H01L2924/01015

Abstract: A conductive polymer-solder ball structure is provided. The conductive polymer-solder ball structure includes a wafer having at least one metal pad providing an electrical conductive path to a substrate layer, a conductive polymer pad located directly on the wafer over the at least one metal pad, an electrolessly plated layer located on a surface of the conductive polymer pad, and a solder ball located on a surface of the electrolessly plated layer.

公开(公告)号：US10043962B2

公开(公告)日：2018-08-07

申请号：US15147595

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Richard S. Graf

IPC: H01L35/30 ,  H01L35/32 ,  H01L35/10 ,  H01L23/38 ,  H01L35/34

Abstract: Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.

公开(公告)号：US09892999B2

公开(公告)日：2018-02-13

申请号：US15175290

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard S. Graf ,  Sudeep Mandal ,  Kibby Horsford

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49579 ,  H01L23/49586 ,  H01L23/49816 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24175 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311

Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

公开(公告)号：US10249590B2

公开(公告)日：2019-04-02

申请号：US15614850

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Sebastian T. Ventrone ,  Richard S. Graf

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L25/065

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.

公开(公告)号：US20170324015A1

公开(公告)日：2017-11-09

申请号：US15147595

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Richard S. Graf

IPC: H01L35/10 ,  H01L35/34 ,  H01L23/38

CPC classification number: H01L35/10 ,  H01L23/38 ,  H01L35/34

Abstract: Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.

公开(公告)号：US09754911B2

公开(公告)日：2017-09-05

申请号：US14875032

申请日：2015-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David J. West ,  Charles H. Wilson ,  Richard S. Graf

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L21/76885 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/90 ,  H01L2021/60022 ,  H01L2224/11505 ,  H01L2224/11552 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/1412 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/15 ,  H01L2224/16113 ,  H01L2224/16168 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/90 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/11442

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with angled interconnect elements. An IC structure according to the present disclosure can include: an IC chip interconnect surface including a radially inner region positioned within a radially outer region; and a plurality of conductive pillars extending outward from the radially inner region of the IC chip interconnect surface, relative to a radial centerline axis of the radially inner region of the IC chip interconnect surface, wherein the radially inner region of the IC chip interconnect surface is free of conductive pillars thereon.

公开(公告)号：US09741695B2

公开(公告)日：2017-08-22

申请号：US14994289

申请日：2016-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Sebastian T. Ventrone

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L24/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/50 ,  H01L29/40 ,  H01L29/41 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/50 ,  H01L2224/73261 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06579 ,  H01L2924/15311

Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

公开(公告)号：US20170098623A1

公开(公告)日：2017-04-06

申请号：US14875032

申请日：2015-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David J. West ,  Charles H. Wilson ,  Richard S. Graf

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L21/76885 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/90 ,  H01L2021/60022 ,  H01L2224/11505 ,  H01L2224/11552 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/1412 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/15 ,  H01L2224/16113 ,  H01L2224/16168 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/90 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/11442

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with angled interconnect elements. An IC structure according to the present disclosure can include: an IC chip interconnect surface including a radially inner region positioned within a radially outer region; and a plurality of conductive pillars extending outward from the radially inner region of the IC chip interconnect surface, relative to a radial centerline axis of the radially inner region of the IC chip interconnect surface, wherein the radially inner region of the IC chip interconnect surface is free of conductive pillars thereon.