公开(公告)号：US20130119555A1

公开(公告)日：2013-05-16

申请号：US13582453

申请日：2011-03-03

申请人： Venkatesh Sundaram ,  Fuhan Liu ,  Rao R. Tummala ,  Vijay Sukumaran ,  Vivek Sridharan ,  Qiao Chen

发明人： Venkatesh Sundaram ,  Fuhan Liu ,  Rao R. Tummala ,  Vijay Sukumaran ,  Vivek Sridharan ,  Qiao Chen

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/562 ,  H01L21/486 ,  H01L21/76843 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/15311

摘要： The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs.

摘要翻译： 本发明一般涉及玻璃作为插入物材料与中间层的表面和/或通孔的壁的应用，其通过提供热膨胀和收缩应力释放以及更好的金属化能力的应力释放屏障来涂覆。 本发明公开了一种应用消除屏障可用于减少不同CTE引起的应力的影响的方法，同时在一些应用中，作为金属化和插入物之间的粘合促进剂。 应力消除屏障用于吸收由不同CTE引起的一些应力，并促进导电金属层的更好的附着力，从而有助于提高可靠性，同时也提供更小的设计。

公开(公告)号：US09275934B2

公开(公告)日：2016-03-01

申请号：US13582453

申请日：2011-03-03

申请人： Venkatesh Sundaram ,  Fuhan Liu ,  Rao Tummala ,  Vijay Sukumaran ,  Vivek Sridharan ,  Qiao Chen

发明人： Venkatesh Sundaram ,  Fuhan Liu ,  Rao Tummala ,  Vijay Sukumaran ,  Vivek Sridharan ,  Qiao Chen

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/486 ,  H01L21/76843 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/15311

摘要： Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.

摘要翻译： 本公开的方面通常涉及包括具有顶部和底部的玻璃插入件中具有壁的多个通孔的微电子封装。 微电子封装还可以在玻璃插入件的顶部和底部的至少一部分上包括应力释放屏障。 微电子封装还可包括在应力消除层的至少一部分上的金属化种子层和金属化种子层的至少一部分上的导体。 导体延伸穿过多个通孔的至少一部分，形成多个金属化的通过封装通孔。 通孔的至少一部分填充有应力消除层或金属化种子层。

公开(公告)号：US08536695B2

公开(公告)日：2013-09-17

申请号：US13415503

申请日：2012-03-08

申请人： Fuhan Liu ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

发明人： Fuhan Liu ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

IPC分类号： H01L23/12 ,  H01L21/4763 ,  H05K1/00 ,  H05K1/03

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/49833 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2224/05599

摘要： The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

摘要翻译： 本发明的各种实施例提供了一种新颖的芯片最后嵌入式结构，其中IC嵌入在一至两个金属层基板内。 本发明的各种实施例与现有技术的其它二维和三维WLFO封装相当，因为实施例具有类似的封装厚度和XY形状因子，短互连长度，到芯片I / O的精细间距互连， 用于将芯片I / O焊盘重新分配到球栅阵列（BGA）或焊盘阵列（LGA）的降低的层数，以及改进的热管理选项。

公开(公告)号：US09173282B2

公开(公告)日：2015-10-27

申请号：US13638536

申请日：2011-03-31

申请人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

发明人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

IPC分类号： H01R9/00 ,  H05K1/02 ,  H01L23/498 ,  H01L25/065 ,  H01R12/52 ,  H01R12/71 ,  H05K3/34 ,  H05K1/18 ,  H05K3/10 ,  H01L29/41 ,  H01L23/13 ,  H01L25/10 ,  H01L23/00

CPC分类号： H05K1/0213 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/413 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/45147 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81385 ,  H01L2224/81399 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/8185 ,  H01L2224/81897 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15791 ,  H01R12/52 ,  H01R12/714 ,  H05K1/18 ,  H05K3/107 ,  H05K3/3436 ,  H05K2201/0248 ,  H05K2201/0281 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/48

摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

摘要翻译： 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（μm）的间距。 互连结构包括介电体元件和提供两个电子部件之间的导电路径的至少一个互连阵列。 每个互连阵列包括提供导电性和整体互连结构的柔性的多条导线。 本发明的互连结构的多功能性和可扩展性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。

公开(公告)号：US20130107485A1

公开(公告)日：2013-05-02

申请号：US13638536

申请日：2011-03-31

申请人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

发明人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh Sundaram ,  Rao R. Tummala

IPC分类号： H05K1/02 ,  H05K3/10 ,  H05K1/18

CPC分类号： H05K1/0213 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/413 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/45147 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81385 ,  H01L2224/81399 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/8185 ,  H01L2224/81897 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15791 ,  H01R12/52 ,  H01R12/714 ,  H05K1/18 ,  H05K3/107 ,  H05K3/3436 ,  H05K2201/0248 ,  H05K2201/0281 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/48

摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

摘要翻译： 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（母体）的间距。 互连结构包括介电体元件和提供两个电子部件之间的导电路径的至少一个互连阵列。 每个互连阵列包括提供导电性和整体互连结构的柔性的多条导线。 本发明的互连结构的多功能性和可扩展性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。

公开(公告)号：US20120228754A1

公开(公告)日：2012-09-13

申请号：US13415503

申请日：2012-03-08

申请人： FUHAN LIU ,  Venkatesh Sundaram ,  Nitesh Kumbhat ,  Rao Tummala

发明人： FUHAN LIU ,  Venkatesh Sundaram ,  Nitesh Kumbhat ,  Rao Tummala

IPC分类号： H01L25/07 ,  H01L23/495

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/49833 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2224/05599

摘要： The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

摘要翻译： 本发明的各种实施例提供了一种新颖的芯片最后嵌入式结构，其中IC嵌入在一至两个金属层基板内。 本发明的各种实施例与现有技术的其它二维和三维WLFO封装相当，因为实施例具有类似的封装厚度和XY形状因子，短互连长度，到芯片I / O的精细间距互连， 用于将芯片I / O焊盘重新分配到球栅阵列（BGA）或焊盘阵列（LGA）的降低的层数，以及改进的热管理选项。

公开(公告)号：US20100270645A1

公开(公告)日：2010-10-28

申请号：US12763433

申请日：2010-04-20

申请人： DAVID ROSS MCGREGOR ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

发明人： DAVID ROSS MCGREGOR ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

IPC分类号： H01L29/86 ,  H01L21/768 ,  H01L21/50 ,  H01L23/522

CPC分类号： H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/1126

摘要： Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

摘要翻译： 提供了包括通过堆积层附着到印刷线路板芯的至少一个薄膜电容器的半导体封装，其中薄膜电容器的第一电极包括薄镍箔，薄膜电容器的第二电极 包括铜电极，并且在镍箔上形成铜层。 薄膜电容器和半导体器件之间的互连提供了将电荷转移到半导体器件和从半导体器件传输电荷的低电感路径。 还提供了制造这种半导体封装的方法。

公开(公告)号：US08391017B2

公开(公告)日：2013-03-05

申请号：US12763433

申请日：2010-04-20

申请人： David Ross McGregor ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

发明人： David Ross McGregor ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

IPC分类号： H01L29/86 ,  H01L21/768 ,  H01L21/50 ,  H01L23/522

CPC分类号： H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/1126

摘要： Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

摘要翻译： 提供了包括通过堆积层附着到印刷线路板芯的至少一个薄膜电容器的半导体封装，其中薄膜电容器的第一电极包括薄镍箔，薄膜电容器的第二电极 包括铜电极，并且在镍箔上形成铜层。 薄膜电容器和半导体器件之间的互连提供了将电荷转移到半导体器件和从半导体器件传输电荷的低电感路径。 还提供了制造这种半导体封装的方法。

公开(公告)号：US20100270646A1

公开(公告)日：2010-10-28

申请号：US12763444

申请日：2010-04-20

申请人： CHEONG-WO HUNTER CHAN ,  Lynne E. Dellis ,  Fuhan Liu ,  David Ross McGregor ,  Venkatesh Sundaram ,  Deepukumar M. Nair

发明人： CHEONG-WO HUNTER CHAN ,  Lynne E. Dellis ,  Fuhan Liu ,  David Ross McGregor ,  Venkatesh Sundaram ,  Deepukumar M. Nair

IPC分类号： H01L29/92 ,  H01L21/50

CPC分类号： H05K1/162 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/1126

摘要： Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

摘要翻译： 提供了包括通过堆积层附着到印刷线路板芯的至少一个薄膜电容器的半导体封装，其中薄膜电容器的第一电极包括薄镍箔，第二电极包括铜电极和 在镍箔上形成铜层。 薄膜电容器和半导体器件之间的互连提供了将电荷转移到半导体器件和从半导体器件传输电荷的低电感路径。 还提供了制造这种半导体封装的方法。

公开(公告)号：US06900708B2

公开(公告)日：2005-05-31

申请号：US10402313

申请日：2003-03-28

申请人： George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

发明人： George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

IPC分类号： H01F17/00 ,  H01F41/04 ,  H01L21/48 ,  H01L25/065 ,  H01L27/08 ,  H01P1/203 ,  H03H7/38 ,  H03F7/00

CPC分类号： H01P1/20381 ,  H01F17/0033 ,  H01F41/041 ,  H01L21/4857 ,  H01L25/0652 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H03H7/38 ,  H01L2924/00

摘要： The present invention includes an organic device that can be integrated in a multilayer board made of organic material. The passive devices can be integrally fabricated on a circuit board in either surface mount device (SMD) or ball grid array (BGA) form. Alternatively, the passive device can be constructed in a stand alone SMD or BGA/chip scale package (CSP) form to make it mountable on a multilayer board, ceramic carrier or silicon platform in the form of an integrated passive device. The passive device includes side shielding on two sides in the SMD form and four sides in the BGA/CSP form. The side shielding can be external or in-built.

摘要翻译： 本发明包括可以集成在由有机材料制成的多层板中的有机器件。 无源器件可以在表面贴装器件（SMD）或球栅阵列（BGA）形式的电路板上整体制造。 或者，无源器件可以以独立的SMD或BGA /芯片级封装（CSP）形式构造，使得其可以以集成的无源器件的形式安装在多层板，陶瓷载体或硅平台上。 无源器件包括SMD形式两侧的侧屏蔽和BGA / CSP形式的四面。 侧面屏蔽可以是外部的或内置的。