公开(公告)号：US20230298959A1

公开(公告)日：2023-09-21

申请号：US18324314

申请日：2023-05-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroyuki KANI ,  Yoshihiro YOSHIMURA ,  Takahiro YAMASHITA ,  Ryo WAKABAYASHI ,  Takashi HIROSE ,  Kiyoshi AIKAWA

IPC: H01L23/367 ,  H04B1/036 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H04B1/04

CPC classification number: H01L23/367 ,  H04B1/036 ,  H01L23/552 ,  H01L23/66 ,  H01L24/09 ,  H01L24/16 ,  H01L23/49827 ,  H01L23/49816 ,  H04B1/04 ,  H04B2001/0408 ,  H01L2223/6611 ,  H01L2223/6661 ,  H01L2224/16227 ,  H01L2224/09515 ,  H01L2924/1421 ,  H01L2924/3025 ,  H01L2223/6616

Abstract: A possible benefit of the present disclosure is to further improve a heat dissipation property of an electronic component. A high-frequency module includes a mounting substrate, a filter (for example, a transmission filter), a resin layer, a shielding layer, and a metal member. The resin layer covers at least a portion of an outer peripheral surface (for example, an outer peripheral surface) of the filter. The shielding layer covers at least a portion of the resin layer. The metal member is disposed at a first principal surface of the mounting substrate. The metal member is connected to a surface of the filter on the opposite side from the mounting substrate, the shielding layer, and the first principal surface of the mounting substrate.

公开(公告)号：US09818707B2

公开(公告)日：2017-11-14

申请号：US14960909

申请日：2015-12-07

Applicant: Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

Inventor： Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/065 ,  H01L27/18 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  G11C7/10

CPC classification number: H01L24/06 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/105 ,  H01L25/0657 ,  H01L27/18 ,  H01L27/222 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L2224/09515 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/1434

Abstract: A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.

公开(公告)号：US20160020185A1

公开(公告)日：2016-01-21

申请号：US14799564

申请日：2015-07-14

Applicant: LAPIS Semiconductor Co., Ltd.

Inventor： Nobutaka NASU

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/06 ,  H01L24/49 ,  H01L27/0251 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06515 ,  H01L2224/0801 ,  H01L2224/09515 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device comprises: a pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes: at least one first pad provided with a first via-connection part electrically connected therewith and extended in a first direction perpendicular to a row direction of the pad row; and at least one second pad provided with a second via-connection part electrically connected therewith and extended in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad.

Abstract translation: 半导体器件包括：焊盘组，其包括设置在半导体衬底上的多个焊盘，并且排列成一行以形成整体的焊盘排。 焊盘组包括：至少一个第一焊盘，其设置有与第一通孔连接部分电连接并沿垂直于焊盘排的行方向的第一方向延伸; 以及至少一个第二垫，其设置有与第一通孔连接部分电连接并沿与​​第一方向相反的第二方向延伸的第二通孔连接部分。 所述至少一个第二垫形成在从穿过所述至少一个第一垫的中心的所述垫排的行方向沿所述第一方向移动的位置。

公开(公告)号：US09208827B2

公开(公告)日：2015-12-08

申请号：US14526802

申请日：2014-10-29

Applicant: SK hynix Inc.

Inventor： Ki Yong Lee ,  Jong Hyun Kim ,  Sang Hwan Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  G11C5/02 ,  H01L25/065 ,  H01L23/00 ,  G11C7/14 ,  H01L23/525 ,  G11C7/10 ,  G11C5/14 ,  G11C29/12

CPC classification number: G11C5/025 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/14 ,  G11C7/20 ,  G11C29/1201 ,  G11C2207/105 ,  H01L23/5256 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0901 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09515 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.

Abstract translation: 半导体堆叠封装可以包括形成有多个耦合焊盘的衬底，堆叠在衬底上的多个半导体芯片。 半导体堆叠封装还可以包括设置在每个半导体芯片上的第一电路单元，并且通过焊盘介质与耦合焊盘电连接。 半导体堆叠封装可以包括设置在每个半导体芯片上并与耦合焊盘电连接的第二电路单元，设置在每个半导体芯片上并对应于第二电路单元的连接焊盘以及耦合在第二电路单元 和连接垫。 半导体堆叠封装还可以包括电连接接合焊盘和耦合焊盘的接合线。

公开(公告)号：US20150302900A1

公开(公告)日：2015-10-22

申请号：US14526802

申请日：2014-10-29

Applicant: SK hynix Inc.

Inventor： Ki Yong LEE ,  Jong Hyun KIM ,  Sang Hwan KIM

IPC: G11C5/02 ,  H01L23/00 ,  G11C29/12 ,  H01L23/525 ,  G11C7/10 ,  G11C5/14 ,  H01L25/065 ,  G11C7/14

CPC classification number: G11C5/025 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/14 ,  G11C7/20 ,  G11C29/1201 ,  G11C2207/105 ,  H01L23/5256 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0901 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09515 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.

Abstract translation: 半导体堆叠封装可以包括形成有多个耦合焊盘的衬底，堆叠在衬底上的多个半导体芯片。 半导体堆叠封装还可以包括设置在每个半导体芯片上的第一电路单元，并且通过焊盘介质与耦合焊盘电连接。 半导体堆叠封装可以包括设置在每个半导体芯片上并与耦合焊盘电连接的第二电路单元，设置在每个半导体芯片上并对应于第二电路单元的连接焊盘以及耦合在第二电路单元 和连接垫。 半导体堆叠封装还可以包括电连接接合焊盘和耦合焊盘的接合线。

公开(公告)号：US20150076703A1

公开(公告)日：2015-03-19

申请号：US14550445

申请日：2014-11-21

Applicant: SK hynix Inc.

Inventor： Chang Kun PARK ,  Seong Hwi SONG ,  Yong Ju KIM ,  Sung Woo HAN ,  Hee Woong SONG ,  Ic Su OH ,  Hyung Soo KIM ,  Tae Jin HWANG ,  Hae Rang CHOI ,  Ji Wang LEE ,  Jae Min JANG

IPC: H01L23/00 ,  H01L27/105

CPC classification number: H01L24/06 ,  H01L23/5286 ,  H01L24/09 ,  H01L27/1052 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/091 ,  H01L2224/09515 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/30101 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

公开(公告)号：US20140346516A1

公开(公告)日：2014-11-27

申请号：US14450359

申请日：2014-08-04

Applicant: Ho-Cheol LEE ,  Chi-Sung OH ,  Jin-Kuk KIM

Inventor： Ho-Cheol LEE ,  Chi-Sung OH ,  Jin-Kuk KIM

IPC: H01L25/065 ,  H01L21/66 ,  H01L27/02 ,  H01L23/00 ,  H01L27/108

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/06 ,  H01L22/32 ,  H01L24/09 ,  H01L24/73 ,  H01L27/0255 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/0912 ,  H01L2224/09179 ,  H01L2224/09515 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract translation: 半导体存储器件包括半导体管芯和输入 - 输出凸块焊盘部分。 半导体管芯包括多个存储单元阵列。 输入输出凸块焊盘部分形成在半导体管芯的中心区域。 输入 - 输出凸块焊盘部件提供多个通道，用于将每个存储单元阵列独立地连接到外部设备。 半导体存储器件可以采用多通道接口，从而具有相对较低功耗的高性能。

公开(公告)号：US08796863B2

公开(公告)日：2014-08-05

申请号：US12891141

申请日：2010-09-27

Applicant: Ho-Cheol Lee ,  Chi-Sung Oh ,  Jin-Kuk Kim

Inventor： Ho-Cheol Lee ,  Chi-Sung Oh ,  Jin-Kuk Kim

IPC: H01L29/12 ,  H01L29/40

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/06 ,  H01L22/32 ,  H01L24/09 ,  H01L24/73 ,  H01L27/0255 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/0912 ,  H01L2224/09179 ,  H01L2224/09515 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract translation: 半导体存储器件包括半导体管芯和输入 - 输出凸块焊盘部分。 半导体管芯包括多个存储单元阵列。 输入输出凸块焊盘部分形成在半导体管芯的中心区域。 输入 - 输出凸块焊盘部件提供多个通道，用于将每个存储单元阵列独立地连接到外部设备。 半导体存储器件可以采用多通道接口，从而具有相对较低功耗的高性能。

公开(公告)号：US12080666B2

公开(公告)日：2024-09-03

申请号：US17665070

申请日：2022-02-04

Applicant: KIOXIA CORPORATION

Inventor： Hideaki Murakami

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/08146 ,  H01L2224/09515 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A semiconductor storage device includes first and second chips. The first chip has first bonding electrodes on a first surface. The second chip has second bonding electrodes on a second surface. The first surface is bonded to the second surface and the first bonding electrodes are electrically connected to the second bonding electrodes. One of the first and second chips has a first bonding pad electrode connectable to a bonding wire for data input/output. A first one of the first bonding electrodes is electrically connected to the first bonding pad electrode. The first chip has, on the first surface, a first insulating layer surrounding the first one of the first bonding electrodes and a second insulating layer that is farther from the first one of the first bonding electrodes than the first insulating layer and formed of a material different from that of the first insulating layer.

公开(公告)号：US20240266341A1

公开(公告)日：2024-08-08

申请号：US18640167

申请日：2024-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/06515 ,  H01L2224/08052 ,  H01L2224/08146 ,  H01L2224/0913 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/48463 ,  H01L2224/8122 ,  H01L2224/81359 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.