公开(公告)号：US20080251494A1

公开(公告)日：2008-10-16

申请号：US12078058

申请日：2008-03-26

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

IPC: H01B13/00 ,  C25D5/34

CPC classification number: C25D7/123 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/108

Abstract: A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed.

Abstract translation: 公开了一种制造电路板的方法。 该方法可以包括：在层叠在载体上的金属层上形成与电路图案对应关系的释放图案; 将载体堆叠并压制到绝缘层上，其中减震图案面向绝缘层; 通过移除载体将金属层和释放图案转印到绝缘层中; 在所述绝缘层上形成通孔，所述绝缘层中所述金属层被转录到所述绝缘层上; 并通过在其上转印有金属层的绝缘层上进行电镀来填充通孔并在金属层上形成镀层。 由于可以在堆叠在载体上的金属层上形成缓和图案，并且可以将缓冲图案转录到绝缘层中，可以形成高密度电路图案。

公开(公告)号：US20080241361A1

公开(公告)日：2008-10-02

申请号：US12007368

申请日：2008-01-09

Applicant: Ji-Hong Jo ,  Myung-Sam Kang

Inventor： Ji-Hong Jo ,  Myung-Sam Kang

IPC: H05K3/02

CPC classification number: H05K3/20 ,  H05K1/0393 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2203/0191 ,  H05K2203/0376 ,  H05K2203/1536

Abstract: A printed circuit board manufacturing method is disclosed. The printed circuit manufacturing method, which includes forming an adhesive layer on a carrier, adhesiveness of the adhesive layer being changed according to heat; forming a circuit pattern on a surface of the adhesive layer; compressing the carrier into the insulation layer to allow the circuit pattern to face the insulation layer; and separating the carrier from the insulation layer by supplying heat to allow the adhesive to reach a predetermined temperature, can reduce a cost of a transferring process and improve the reliability of products by minimizing the affect on a metal pattern, by using a material having the adhesiveness changed according to the temperature as an adhesive layer.

Abstract translation: 公开了印刷电路板的制造方法。 印刷电路制造方法，其包括在载体上形成粘合剂层，粘合剂层的粘合性根据热而改变; 在粘合剂层的表面上形成电路图案; 将载体压缩到绝缘层中以允许电路图案面向绝缘层; 并通过供应热量使粘合剂达到预定温度而将载体与绝缘层分离，可以通过使用具有以下特征的材料来降低对金属图案的影响，从而降低了转印过程的成本并提高了产品的可靠性 粘合性根据作为粘合层的温度而变化。

公开(公告)号：US20080212299A1

公开(公告)日：2008-09-04

申请号：US11797084

申请日：2007-04-30

Applicant: Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

Inventor： Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

IPC: H05K1/18 ,  H01R43/00

CPC classification number: H05K1/162 ,  H05K3/205 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/09672 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: Disclosed are a printed circuit board for improving the tolerance of embedded capacitors and a method of manufacturing the same. The printed circuit board having embedded capacitors is manufactured by transferring and embedding a circuit layer having a lower electrode formed through an additive process into a resin insulating layer, and thereby is minimized in the circuit tolerance conventionally caused by an etching process to thus be applied to capacitors for RF matching.

Abstract translation: 公开了一种用于提高嵌入式电容器的容限的印刷电路板及其制造方法。 具有嵌入式电容器的印刷电路板通过将具有通过添加工艺形成的下电极的电路层转移并嵌入到树脂绝缘层中而被制造，从而在通常由蚀刻工艺引起的电路公差中被最小化，从而被应用于 电容器用于RF匹配。

公开(公告)号：US20080115355A1

公开(公告)日：2008-05-22

申请号：US11984209

申请日：2007-11-14

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang

IPC: H05K3/10 ,  H01K3/10

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/205 ,  H05K2201/0394 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  H05K2203/0542 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a printed circuit board is disclosed. Using the method, which includes embedding a first circuit pattern and a second circuit pattern in one side and the other side of an insulation substrate, forming a via hole by removing portions of the insulation substrate and the first circuit pattern, and electrically connecting the first circuit pattern and the second circuit pattern by forming a plating layer in the via hole, it is possible to form high-density circuits, as circuitry may be formed in portions that might have been occupied by lands, and more circuitry may be implemented for a given area of insulation substrate, whereby a fine-patterned printed circuit board may be implemented that has a high degree of integration. Also, a printed circuit board can be produced which allows good signal transfers between layers and with which fine circuit patterns can be implemented with inexpensive costs.

Abstract translation: 公开了一种制造印刷电路板的方法。 使用该方法，其包括在绝缘基板的一侧和另一侧嵌入第一电路图案和第二电路图案，通过去除绝缘基板和第一电路图案的部分而形成通孔，并且将第一 电路图案和第二电路图案，通过在通孔中形成镀层，可以形成高密度电路，因为电路可以形成为可能已经被焊盘占据的部分，并且可以实现更多的电路用于 可以实现具有高度集成度的精细图案化印刷电路板。 此外，可以制造印刷电路板，其可以在层之间进行良好的信号传输，并且可以以廉价的成本实现精细的电路图案。

公开(公告)号：US20080009128A1

公开(公告)日：2008-01-10

申请号：US11708339

申请日：2007-02-21

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/44

CPC classification number: H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

Abstract: A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.

Abstract translation: 公开了掩埋图案基板及其制造方法。 一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在 晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘 不必要，并且通孔的尺寸小，以允许电路中的较高密度。

公开(公告)号：US20070290344A1

公开(公告)日：2007-12-20

申请号：US11783871

申请日：2007-04-12

Applicant: Myung-Sam Kang ,  Byoung-Youl Min ,  Joon-Sung Kim ,  Je-Gwang Yoo ,  Jong-Gyu Choi

Inventor： Myung-Sam Kang ,  Byoung-Youl Min ,  Joon-Sung Kim ,  Je-Gwang Yoo ,  Jong-Gyu Choi

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0394 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a printed circuit board, and in particular, to a printed circuit board for a package of electronic components and manufacturing method thereof. One aspect of present invention provides a manufacturing method of a printed circuit board for an electronic component package, which includes: forming a circuit pattern including bonding pads on one side of a first insulation layer, laminating a second insulation layer onto one side of the first insulation layer, and exposing the bonding pads by removing a part of the first insulation layer and the second insulation layer corresponding to the location in which the bonding pads is formed.

Abstract translation: 印刷电路板技术领域本发明涉及一种印刷电路板，特别涉及一种电子元件封装用印刷电路板及其制造方法。 本发明的一个方面提供了一种用于电子部件封装的印刷电路板的制造方法，其包括：形成包括在第一绝缘层的一侧上的焊盘的电路图案，将第二绝缘层层压到第一绝缘层的一侧上 绝缘层，并且通过去除与形成接合焊盘的位置相对应的第一绝缘层和第二绝缘层的一部分来暴露接合焊盘。

公开(公告)号：US20070059918A1

公开(公告)日：2007-03-15

申请号：US11520730

申请日：2006-09-14

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H01L21/4763

CPC classification number: H05K3/4691 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K1/189 ,  H05K3/4623 ,  H05K2201/056 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/063 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention relates to a rigid-flexible multi-layer printed circuit board comprising: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. According the present invention, when the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

Abstract translation: 硬质柔性多层印刷电路板技术领域本发明涉及一种柔性多层印刷电路板，包括：柔性基板，其两侧形成有可弯曲的电路; 层叠在柔性基板上的刚性基板和电路形成在两侧，并且形成有安装半导体芯片的空腔; 以及粘合柔性基板和刚性基板并具有绝缘性的粘合片。 根据本发明，当安装相同数量的半导体芯片或实施POP时，封装的整体厚度可以较低。 此外，可以使用空间作为芯层的厚度来安装另外两个半导体芯片，并且可以实现当传统技术中安装在底部基板上的半导体芯片的数量变为二倍时的结构不可行。

公开(公告)号：US07015691B2

公开(公告)日：2006-03-21

申请号：US10639285

申请日：2003-08-12

Applicant: Myung-Sam Kang ,  Sang-On Choi ,  Won-Youl Choi ,  Jang-Kyu Kang

Inventor： Myung-Sam Kang ,  Sang-On Choi ,  Won-Youl Choi ,  Jang-Kyu Kang

IPC: G01R33/04

CPC classification number: G01R33/045 ,  G01R15/185 ,  H01F5/003 ,  Y10T29/49073

Abstract: In a weak-magnetic field sensor a rectangular ring-shaped magnetic core is wound by exciting circuit patterns and detecting circuit patterns, and weak-magnetic field sensors are implemented in x-axis and y-axis directions, respectively, to precisely calculate azimuth, thereby sensing a weak-magnetic field having a strength similar to that of earth's magnetic field. The sensor includes a magnetic core having first and second cores connected in parallel to each other; exciting coils wound around the first and second cores, respectively, to supply alternating excitation current to the magnetic core; and a detecting coil alternately arranged together with the exciting coils on the same surfaces on which the exciting coils are formed, and wound around the first and second cores, in order to detect variation of magnetic fluxes generated in the magnetic core.

Abstract translation: 在弱磁场传感器中，通过激励电路图案和检测电路图案缠绕矩形环形磁芯，分别在x轴和y轴方向上实现弱磁场传感器，以精确计算方位角， 从而感测到具有与地球磁场强度类似的强度的弱磁场。 传感器包括具有彼此并联连接的第一和第二芯的磁芯; 励磁线圈分别缠绕在第一和第二芯上，以向磁芯提供交替的激励电流; 以及检测线圈，与励磁线圈交替布置在其上形成有励磁线圈的相同表面上，并缠绕在第一和第二芯上，以便检测在磁芯中产生的磁通量的变化。

公开(公告)号：US06753682B2

公开(公告)日：2004-06-22

申请号：US10139356

申请日：2002-05-07

Applicant: Myung-Sam Kang ,  Kyoung-Won Na ,  Sang-On Choi ,  Won-Youl Choi ,  Jeong-Hwan Lee ,  Keon-Yang Park

Inventor： Myung-Sam Kang ,  Kyoung-Won Na ,  Sang-On Choi ,  Won-Youl Choi ,  Jeong-Hwan Lee ,  Keon-Yang Park

IPC: G01R3304

CPC classification number: G01C17/30 ,  G01R33/05 ,  H05K1/165

Abstract: A weak-magnetic field sensor using printed circuit board manufacturing technique which detects the Earth's magnetic field to obtain positional information, and a method of manufacturing the same is disclosed. The sensor comprises a first base board which is formed at its upper and lower surfaces with first driving patterns and first pickup patterns, a pair of first stacked boards which are stacked on upper and lower surfaces of the first base board and which are formed with magnetic layers thereon, and a pair of second stacked boards which are stacked on outer surfaces of the pair of first stacked boards and which are formed with second driving patterns and second pickup patterns electrically connected to the first driving patterns and the first pickup patterns of the first base board to surround magnetic layers. The magnetic layer, the driving patterns and the pickup patterns provided on the first base board are oriented to be perpendicular to those provided under the first base board.

Abstract translation: 公开了使用检测地球磁场以获得位置信息的印刷电路板制造技术的弱磁场传感器及其制造方法。 传感器包括：第一基板，其在其上表面和下表面上形成有第一驱动图案和第一拾取图案;一对第一堆叠板，其堆叠在第一基板的上表面和下表面上，并且形成有磁性 层叠在一起的一对第二堆叠板和堆叠在一对第一堆叠板的外表面上并且形成有第二驱动图案和电连接到第一驱动图案的第二拾取图案和第一驱动图案的第一拾取图案 基板以环绕磁层。 设置在第一基板上的磁性层，驱动图案和拾取图案被定向为垂直于设置在第一基板下方的磁性层。

公开(公告)号：US06582616B2

公开(公告)日：2003-06-24

申请号：US09984284

申请日：2001-10-29

Applicant: Myung-Sam Kang ,  Keon-Yang Park ,  Won-Hoe Kim

Inventor： Myung-Sam Kang ,  Keon-Yang Park ,  Won-Hoe Kim

IPC: H01B1300

CPC classification number: H01L21/4803 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/4611 ,  Y10T29/49155 ,  Y10T29/49169 ,  H01L2924/00

Abstract: Disclosed are a method for preparing a high performance BGA board containing a plurality of printed circuit boards in which a conductor circuit, a bonding pad electrically connected to a semiconductor chip, and an inner hole for mounting a semiconductor chip are formed, by primary- and secondary-laminating a plurality of boards. The present invention enjoys advantages in that contamination due to an outer layer surface treatment of the board laminate can be prevented, and a process for preventing a contamination of an inner hole can be omitted, and also a defective proportion can be reduced remarkably in comparison with prior arts by applying a pressure uniformly during a secondary lamination. Furthermore, a BGA board according to the invention has an ideal ball pitch and multi-fins, excellent electrical and thermal properties, also can be applied in the case of high current, and can be easily mounted on a chip.