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    SYSTEM FOR COMPRESSING FLOATING POINT DATA
    93.
    发明申请
    SYSTEM FOR COMPRESSING FLOATING POINT DATA 审中-公开

    公开(公告)号：US20190044531A1

    公开(公告)日：2019-02-07

    申请号：US15977720

    申请日：2018-05-11

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Kirk S. Yap ,  Olivia K. Wu

    IPC: H03M7/24 ,  H03M7/30 ,  G06F12/0802

    Abstract: A processor comprises a first memory to store data elements that are encoded according to a floating point format including a sign field, an exponent field, and a significand field; and a compression engine comprising circuitry, the compression engine to generate a compressed data block that is to include a tag type per data element, wherein responsive to a determination that a first data element includes a value in its exponent field that does not match a value of any entry in a dictionary, a first tag type and an uncompressed value of the data element are included in the compressed data block; and responsive to a determination that a second data element includes a value in its exponent field that matches a value of a first entry in the dictionary, a second tag type and a compressed value of the data element are included in the compressed data block.

    Double affine mapped S-box hardware accelerator
    94.
    发明授权
    Double affine mapped S-box hardware accelerator 有权

    公开(公告)号：US10158485B2

    公开(公告)日：2018-12-18

    申请号：US14863769

    申请日：2015-09-24

    Applicant: Intel Corporation

    Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Vinodh Gopal ,  Kirk S. Yap

    IPC: H04L9/10 ,  G09C1/00 ,  H04L9/06 ,  G06F7/72

    Abstract: A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.

    Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
    97.
    发明授权
    Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction 有权

    公开(公告)号：US10042639B2

    公开(公告)日：2018-08-07

    申请号：US15397678

    申请日：2017-01-03

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC: G06F9/00 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F7/544

    Abstract: According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.

    METHOD AND APPARATUS FOR HYBRID COMPRESSION PROCESSING FOR HIGH LEVELS OF COMPRESSION
    98.
    发明申请
    METHOD AND APPARATUS FOR HYBRID COMPRESSION PROCESSING FOR HIGH LEVELS OF COMPRESSION 审中-公开

    公开(公告)号：US20180159551A1

    公开(公告)日：2018-06-07

    申请号：US15816959

    申请日：2017-11-17

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Daniel F. Cutter

    IPC: H03M7/30 ,  G06F3/06

    CPC classification number: H03M7/3086 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0673 ,  H03M7/3068 ,  H03M7/6017

    Abstract: In one embodiment, an apparatus comprises a first compression engine to receive a first compressed data block from a second compression engine that is to generate the first compressed data block by compressing a first plurality of repeated instances of data that each have a length greater than or equal to a first length. The first compression engine is further to compress a second plurality of repeated instances of data of the first compressed data block that each have a length greater than or equal to a second length, the second length being shorter than the first length, wherein each compressed repeated instance of the first and second pluralities of repeated instances comprises a location and length of a data instance that is repeated. The apparatus further comprises a memory buffer to store the compressed first and second plurality of repeated instances of data.

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