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    TRENCH JUNCTION BARRIER CONTROLLED SCHOTTKY
    94.
    发明申请
    TRENCH JUNCTION BARRIER CONTROLLED SCHOTTKY 有权
    TRENCH JUNCTION BARRIER控制的肖特

    公开(公告)号：US20140332882A1

    公开(公告)日：2014-11-13

    申请号：US13892312

    申请日：2013-05-13

    申请人： SiK K. Lui ,  Anup Bhalla

    发明人： SiK K. Lui ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872

    摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

    摘要翻译： 一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。

    Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method
    97.
    发明申请
    Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method 有权
    具有多个嵌入式电位扩展结构的端接结构，用于沟槽MOSFET和方法

    公开(公告)号：US20140167212A1

    公开(公告)日：2014-06-19

    申请号：US13712980

    申请日：2012-12-13

    申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

    发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

    IPC分类号： H01L21/762 ,  H01L29/06

    CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

    摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

    MOS device with Schottky barrier controlling layer
    99.
    发明授权
    MOS device with Schottky barrier controlling layer 有权
    具有肖特基势垒控制层的MOS器件

    公开(公告)号：US08362547B2

    公开(公告)日：2013-01-29

    申请号：US12005166

    申请日：2007-12-21

    申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

    发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7811 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/8725

    摘要： A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body into the drain region; an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain region form a Schottky diode; and a Schottky barrier controlling layer.

    摘要翻译： 形成在半导体衬底上的半导体器件包括：覆盖半导体衬底的外延层; 在半导体衬底背面形成的漏极; 漏极区域，其延伸到所述外延层中; 和活跃区域。 有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区域接触沟槽，其延伸穿过所述源极和所述本体进入所述漏极区域; 有源区接触电极，设置在有源区接触沟槽内，其中有源区接触电极和漏区形成肖特基二极管; 和肖特基势垒控制层。

    POWER MOS DEVICE FABRICATION
    100.
    发明申请
    POWER MOS DEVICE FABRICATION 有权
    电源MOS器件制造

    公开(公告)号：US20120329225A1

    公开(公告)日：2012-12-27

    申请号：US13604286

    申请日：2012-09-05

    申请人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

    发明人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

    摘要： Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.

    摘要翻译： 制造半导体器件包括在具有顶部衬底表面的衬底上形成掩模; 通过掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 取下面罩离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 在源体接触沟槽中形成插塞，其中插头延伸到身体区域的底部下方; 并且在所述源体接触沟槽中，在所述插头的顶部上设置导电材料。