公开(公告)号：US5155738A

公开(公告)日：1992-10-13

申请号：US606812

申请日：1990-10-31

Applicant: Teturo Ijichi ,  Hiroshi Okamoto

Inventor： Teturo Ijichi ,  Hiroshi Okamoto

IPC: H01S5/20 ,  H01S5/223 ,  H01S5/34 ,  H01S5/343

CPC classification number: B82Y20/00 ,  H01S5/34313 ,  H01S5/209 ,  H01S5/223 ,  H01S5/2231 ,  H01S5/3406

Abstract: A semiconductor laser element having a GaAs substrate formed thereon with an active layer of a strained quantum well construction provided with an In.sub.x Ga.sub.1-x As strained quantum well layer and a GaAs barrier layer and clad layers arranged up and down of said active layer through an epitaxial growth means. A lattice mismatching rate of the clad layer with respect to the substrate is less than 10.sup.-3.

公开(公告)号：US5021360A

公开(公告)日：1991-06-04

申请号：US412354

申请日：1989-09-25

Applicant: Paul Melman ,  Boris S. Elman ,  Emil S. Koteles ,  Chirravuri Jagannath

Inventor： Paul Melman ,  Boris S. Elman ,  Emil S. Koteles ,  Chirravuri Jagannath

IPC: H01L29/06 ,  H01L21/20 ,  H01L21/203 ,  H01L29/205 ,  H01S5/34

CPC classification number: B82Y20/00 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01S5/34 ,  H01S5/3403 ,  H01S5/3406 ,  Y10S148/06 ,  Y10S148/097 ,  Y10S148/16 ,  Y10S438/936 ,  Y10S438/938

Abstract: A method of fabricating a semiconductor heterostructure includes the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. A buffer layer having a thickness above a critical value is grown on the substrate whereby the stress due to a lattice constant mismatch between the buffer layer and substrate is relieved through the formation of misfit dislocations. A strained superlattice structure is grown on the buffer layer in order to terminate any upwardly-propagating dislocations. An unstrained barrier layer is subsequently grown on the superlattice structure. The fabrication method concludes with the growth of a quantum well structure on the unstrained layer wherein a lattice constant mismatch between the quantum well structure and the unstrained barrier layer is smaller than the lattice constant mismatch between the quantum well structure and the substrate. As a result, only a fraction of the stress due to the large lattice mismatch between the quantum well structure and the substrate is accommodated by coherent strain in the quantum well structure, while the remainder of the stress is relieved through the formation of misfit dislocations spatially separated from the quantum well structure.

公开(公告)号：US4866489A

公开(公告)日：1989-09-12

申请号：US076549

申请日：1987-07-22

Applicant: Toshiya Yokogawa ,  Mototsugu Ogura

Inventor： Toshiya Yokogawa ,  Mototsugu Ogura

IPC: G02F1/017 ,  G02F1/355 ,  G02F1/37 ,  H01L27/146 ,  H01S5/02 ,  H01S5/026 ,  H01S5/20 ,  H01S5/32 ,  H01S5/34 ,  H01S5/347

CPC classification number: B82Y20/00 ,  G02F1/3556 ,  H01L27/14665 ,  H01S5/026 ,  H01S5/347 ,  G02F1/37 ,  G02F2001/01766 ,  H01S2301/173 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/2004 ,  H01S5/3201 ,  H01S5/3406 ,  H01S5/3409

Abstract: A semiconductor device in which a strained-layer of super-lattice composed of two or more group II-IV semiconductors grown on an epitaxial growth layer formed on a surface of a semiconductor substrate. Since the strained-layer of super-lattice composed of two or more group II-VI semiconductors is present in the heterojunction of the heterostructure, it is possible to form a favorable heterostructure seminconductor layer, inhibiting the adverse effects of lattice mismatch.

Abstract translation: 一种半导体器件，其中在形成在半导体衬底的表面上的外延生长层上生长的由两个或更多个II-IV族半导体组成的超晶格的应变层。 由于由两个以上的II-VI族II族半导体构成的超晶格的应变层存在于异质结构的异质结中，因此可以形成有利的异质结晶半导体层，抑制晶格失配的不利影响。

公开(公告)号：US11843224B2

公开(公告)日：2023-12-12

申请号：US17392305

申请日：2021-08-03

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Takashi Kato

IPC: H01S5/34 ,  H01S5/343

CPC classification number: H01S5/3406 ,  H01S5/3402 ,  H01S5/34313 ,  H01S5/34346

Abstract: A quantum cascade laser includes a substrate having a group III-V compound semiconductor and a core region that is provided on the substrate and that includes a group III-V compound semiconductor. The core region includes a plurality of unit structures that are stacked on top of one another. Each of the plurality of unit structures includes an active layer and an injection layer. The injection layer includes at least one strain-compensated layer including a first well layer and a first barrier layer and at least one lattice-matched layer including a second well layer and a second barrier layer. The first well layer has a lattice constant larger than a lattice constant of the substrate. The first barrier layer has a lattice constant smaller than the lattice constant of the substrate. The second well layer and the second barrier layer each have a lattice constant that is lattice-matched to the substrate.

公开(公告)号：US20180366418A1

公开(公告)日：2018-12-20

申请号：US15962474

申请日：2018-04-25

Applicant: WIN Semiconductors Corp.

Inventor： Chang-Hwang HUA ,  Wen CHU

IPC: H01L23/00 ,  H01L29/45 ,  H01S5/024 ,  H01S5/042 ,  H01S5/02 ,  H01S5/34 ,  H01L23/373

CPC classification number: H01L23/562 ,  H01L23/367 ,  H01L23/373 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/45 ,  H01L29/452 ,  H01L29/861 ,  H01L29/866 ,  H01L29/872 ,  H01L33/12 ,  H01L33/40 ,  H01L2933/0016 ,  H01S5/0206 ,  H01S5/02476 ,  H01S5/0425 ,  H01S5/18311 ,  H01S5/18344 ,  H01S5/187 ,  H01S5/3201 ,  H01S5/3406 ,  H01S2301/173

Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.

公开(公告)号：US20180109076A1

公开(公告)日：2018-04-19

申请号：US15832248

申请日：2017-12-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Toru TAKAYAMA

IPC: H01S5/22 ,  H01S5/34 ,  H01S5/343

CPC classification number: H01S5/2206 ,  G03B21/2033 ,  H01S5/2009 ,  H01S5/22 ,  H01S5/305 ,  H01S5/3063 ,  H01S5/3201 ,  H01S5/3211 ,  H01S5/3406 ,  H01S5/34333 ,  H01S2301/173

Abstract: A light emitting element according to the present disclosure includes: a GaN substrate; a first strain correction layer disposed above the GaN substrate and including InxGa1-xN of a first conductivity type where x is greater than 0 and less than or equal to 1; a first low refractive index layer disposed above the first strain correction layer, including In1-a-bGaaAlbN of the first conductivity type, and having relationships of (a/0.98)+(b/0.8)≥1, (a/1.02)+(b/0.85)≤1, and (a/1.03)+(b/0.68)≥1; a first clad layer disposed above the first low refractive index layer, including AlxGa1-xN of the first conductivity type where z is greater than or equal to 0.03 and less than or equal to 0.06, and having a refractive index higher than a refractive index of the first low refractive index layer; and an active layer disposed above the first clad layer.

公开(公告)号：US09793686B2

公开(公告)日：2017-10-17

申请号：US15099906

申请日：2016-04-15

Applicant: UCL Business PLC

Inventor： Huiyun Liu ,  Andrew David Lee ,  Alwyn John Seeds

IPC: H01S5/00 ,  H01S5/34 ,  H01S5/02 ,  H01S5/30 ,  H01S5/20 ,  H01S5/343 ,  H01L21/02 ,  B82Y20/00

CPC classification number: H01S5/3412 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02661 ,  H01S5/02 ,  H01S5/021 ,  H01S5/2018 ,  H01S5/3013 ,  H01S5/34 ,  H01S5/3403 ,  H01S5/3406 ,  H01S5/343 ,  H01S5/34313

Abstract: A semiconductor device comprising a silicon substrate on which is grown a

公开(公告)号：US09570888B1

公开(公告)日：2017-02-14

申请号：US15177956

申请日：2016-06-09

Applicant: Soraa Laser Diode, Inc.

Inventor： James W. Raring ,  Christiane Poblenz Elsass

IPC: H01L21/00 ,  H01S5/343 ,  H01S5/22 ,  H01S5/20 ,  H01S5/30 ,  H01S5/32 ,  H01S5/34

CPC classification number: H01S5/34333 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/16 ,  H01L33/32 ,  H01S5/1082 ,  H01S5/2009 ,  H01S5/2018 ,  H01S5/2031 ,  H01S5/2201 ,  H01S5/3063 ,  H01S5/3201 ,  H01S5/3202 ,  H01S5/3213 ,  H01S5/3406 ,  H01S5/34346

Abstract: An optical device has a gallium and nitrogen containing substrate including a surface region and a strain control region, the strain control region being configured to maintain a quantum well region within a predetermined strain state. The device also has a plurality of quantum well regions overlying the strain control region.

Abstract translation: 光学装置具有包含表面区域和应变控制区域的含有氮化镓和氮的衬底，所述应变控制区域被配置为将量子阱区域保持在预定的应变状态。 该装置还具有覆盖在应变控制区域上的多个量子阱区域。

公开(公告)号：US09343874B2

公开(公告)日：2016-05-17

申请号：US14418399

申请日：2013-07-30

Applicant: UCL BUSINESS PLC

Inventor： Huiyun Liu ,  Andrew David Lee ,  Alwyn John Seeds

IPC: H01S5/00 ,  H01S5/34 ,  H01S5/02 ,  H01S5/30 ,  H01S5/20 ,  H01S5/343 ,  H01L21/02 ,  B82Y20/00

CPC classification number: H01S5/3412 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02661 ,  H01S5/02 ,  H01S5/021 ,  H01S5/2018 ,  H01S5/3013 ,  H01S5/34 ,  H01S5/3403 ,  H01S5/3406 ,  H01S5/343 ,  H01S5/34313

Abstract: A semiconductor device comprising a silicon substrate on which is grown a

Abstract translation: 一种半导体器件，包括硅衬底，在其上生长厚度<100nm厚的AlAs或相关化合物的外延层，之后是除GaN缓冲层之外的化合物半导体。 另外的III-V族化合物半导体结构可以在顶部外延生长。 AlAs外延层减少了与硅的界面的缺陷的形成和传播，因此可以改善在顶部生长的活性结构的性能。

公开(公告)号：US20150311676A1

公开(公告)日：2015-10-29

申请号：US14795387

申请日：2015-07-09

Applicant: FURUKAWA ELECTRIC CO., LTD.

Inventor： Junji YOSHIDA ,  Hirokazu ITOH ,  Satoshi IRINO ,  Yuichiro IRIE ,  Taketsugu SAWAMURA

IPC: H01S5/32 ,  H01S5/34 ,  H01S5/20

CPC classification number: H01S5/3216 ,  B82Y20/00 ,  H01S3/04 ,  H01S3/0675 ,  H01S3/06754 ,  H01S3/094003 ,  H01S3/094011 ,  H01S3/09415 ,  H01S3/302 ,  H01S5/0064 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/024 ,  H01S5/0287 ,  H01S5/1039 ,  H01S5/1064 ,  H01S5/146 ,  H01S5/2018 ,  H01S5/2077 ,  H01S5/2205 ,  H01S5/2206 ,  H01S5/2222 ,  H01S5/227 ,  H01S5/3213 ,  H01S5/34 ,  H01S5/3406 ,  H01S5/34306 ,  H01S5/3434 ,  H01S2301/03 ,  H01S2301/166

Abstract: An optical semiconductor device outputting a predetermined wavelength of laser light includes: a quantum well active layer positioned between a p-type cladding layer and an n-type cladding layer in thickness direction; a separate confinement heterostructure layer positioned between the quantum well active layer and the n-type cladding layer; and an electric-field-distribution-control layer positioned between the separate confinement heterostructure layer and the n-type cladding layer and configured by at least two semiconductor layers having band gap energy greater than band gap energy of a barrier layer constituting the quantum well active layer.