公开(公告)号：US20150195908A1

公开(公告)日：2015-07-09

申请号：US14661665

申请日：2015-03-18

Applicant: FUJIFILM CORPORATION

Inventor： Yasuaki MATSUSHITA ,  Tokihiko MATSUMURA

IPC: H05K1/03 ,  H05K1/09

CPC classification number: H05K1/0353 ,  H05K1/092 ,  H05K3/247 ,  H05K2201/0769

Abstract: A wiring board includes: an insulating substrate; and a wiring layer including a first metal layer disposed on the insulating substrate and a second metal layer disposed so as to cover a surface of the first metal layer, the surface not being in contact with the insulating substrate, wherein the thickness of the second metal layer is 1/10 of the total thickness of the wiring layer, the wiring layer contains a migration inhibitor, and the mass Y of the migration inhibitor contained in the second metal layer is greater than the mass X of the migration inhibitor contained in the first metal layer.

Abstract translation: 布线基板包括：绝缘基板; 以及布置层，其包括设置在绝缘基板上的第一金属层和设置成覆盖第一金属层的表面的第二金属层，该表面不与绝缘基板接触，其中第二金属 层是布线层的总厚度的1/10，布线层含有迁移抑制剂，第二金属层中含有的迁移抑制剂的质量Y大于第一金属层中所含的迁移抑制剂的质量X. 金属层。

公开(公告)号：US20150138739A1

公开(公告)日：2015-05-21

申请号：US14520973

申请日：2014-10-22

Applicant: NITTO DENKO CORPORATION

Inventor： Tomoaki HISHIKI

IPC: H05K3/30 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K3/305 ,  G11B5/4826 ,  G11B5/484 ,  G11B5/4853 ,  H05K3/321 ,  H05K2201/0769 ,  H05K2201/10977 ,  Y02P70/613

Abstract: A suspension board with circuit includes an electronic element, and a mounting portion having a terminal portion electrically connected to the electronic element. The electronic element and the mounting portion are bonded to each other via an adhesive containing a metal ion scavenger.

Abstract translation: 具有电路的悬挂板包括电子元件和具有电连接到电子元件的端子部分的安装部分。 电子元件和安装部分通过含有金属离子清除剂的粘合剂相互结合。

公开(公告)号：US20150116961A1

公开(公告)日：2015-04-30

申请号：US14066689

申请日：2013-10-30

Applicant: Lakshminarayan Viswanathan

Inventor： Lakshminarayan Viswanathan

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0256 ,  H05K2201/0769 ,  H05K2201/09781 ,  Y10T29/49117

Abstract: A circuit includes a structure for inhibiting dendrite formation. The circuit includes a first electrode disposed within a first area of the circuit, wherein the first electrode is configured to be coupled to an ionic source that forms ions when a first electric potential is applied to the first electrode. The circuit also includes a second electrode disposed within a second area of the circuit. The second electrode is configured to receive a second electric potential that is less than the first electric potential and that causes the ions to migrate toward the second electrode to contribute to dendrite formation. The circuit further includes a structure disposed within a third area of the circuit. The structure is configured to receive a third electric potential to create a barrier that inhibits the migration of at least some of the ions from the first to the second electrode to inhibit dendrite formation.

Abstract translation: 电路包括抑制枝晶形成的结构。 电路包括设置在电路的第一区域内的第一电极，其中第一电极被配置为耦合到当向第一电极施加第一电位时形成离子的离子源。 电路还包括设置在电路的第二区域内的第二电极。 第二电极被配置为接收小于第一电位的第二电位并且导致离子朝向第二电极迁移以有助于枝晶形成。 电路还包括设置在电路的第三区域内的结构。 该结构被配置为接收第三电位以产生阻挡至少一些离子从第一电极到第二电极迁移以阻止枝晶形成的屏障。

公开(公告)号：US08907225B1

公开(公告)日：2014-12-09

申请号：US14221833

申请日：2014-03-21

Applicant: The United States of America as represented by the Secretary of the Navy

Inventor： Nishkamraj U Deshpande ,  H. Fred Barsun ,  Ron Shoultz

IPC: H05K1/02 ,  H05K3/28 ,  H01L23/31 ,  H05K3/30

CPC classification number: H05K1/0275 ,  H05K3/28 ,  H05K2201/0251 ,  H05K2201/026 ,  H05K2201/0769 ,  H05K2201/09872 ,  H05K2203/161 ,  Y10T29/49146 ,  Y10T428/1405

Abstract: A method and an apparatus for mitigating electrical failures caused by intrusive structures. Such structures can be tin whiskers forming on electrical circuits. In an illustrative embodiment, nano-capsules are filled with some type of insulative and adhesive fluid that is adapted to bind to and coat an intrusive structure, e.g., a whisker, making the whisker electrically inactive and thereby reducing the electrical faults that can be caused by the whisker. In another illustrative embodiment, randomly oriented nano-fibers having an elastic modulus higher than tin or any other whisker material is used to arrest a growth or movement of a whisker and further reduce a likelihood that a whisker can cause an electrical fault.

Abstract translation: 一种用于减轻由侵入式结构引起的电气故障的方法和装置。 这种结构可以是在电路上形成的锡晶须。 在说明性实施例中，纳米胶囊填充有某种类型的绝缘和粘合剂流体，其适于结合并涂覆侵入结构（例如晶须），使晶须电不活动，从而减少可能引起的电气故障 由晶须 在另一个说明性实施例中，使用弹性模量高于锡或任何其它晶须材料的随机取向的纳米纤维来阻止晶须的生长或移动，并进一步降低晶须可能导致电气故障的可能性。

公开(公告)号：US08821708B2

公开(公告)日：2014-09-02

申请号：US12089025

申请日：2006-10-02

Applicant: Masanobu Tsujimoto ,  Isamu Yanada ,  Katsuaki Suganuma ,  Keunsoo Kim

Inventor： Masanobu Tsujimoto ,  Isamu Yanada ,  Katsuaki Suganuma ,  Keunsoo Kim

IPC: C25D5/02 ,  C25D5/00 ,  C25D5/10 ,  H05K3/24 ,  C25D7/00 ,  B32B15/01 ,  H01R13/03

CPC classification number: C25D5/10 ,  B32B15/01 ,  B32B15/018 ,  C22C13/00 ,  C22C13/02 ,  C25D5/02 ,  C25D7/00 ,  H01L2924/0002 ,  H01R13/03 ,  H05K3/244 ,  H05K2201/0347 ,  H05K2201/0769 ,  H01L2924/00

Abstract: A surface treatment method of cladding a Sn or Sn alloy coating with one or more metals selected from among Mn, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Ga, In, Ti, Ge, Pb, Sb and Bi continuously or discontinuously in such a way as to make the Sn or Sn alloy coating partially exposed, which method makes it possible to inhibit the generation of whiskers in an Sn or Sn alloy coating formed on the surface of a substrate to which other member is pressure-welded or the joint surface to be soldered. Cladding an Sn or Sn alloy coating with a prescribed metal continuously or discontinuously in such a way as to make the coating partially exposed inhibits the generation of whiskers by contact pressure in pressure welding, and further inhibits the generation of whiskers without impairing the solder wettability of the coating even when the cladding is not followed by heat treatment or reflowing.

Abstract translation: 一种用一种或多种选自Mn，Fe，Ru，Os，Co，Rh，Ir，Ni，Pd，Pt，Cu，Ag，Au，Zn，Cd中的一种或多种金属包覆Sn或Sn合金涂层的表面处理方法， Ga，In，Ti，Ge，Pb，Sb和Bi，以使Sn或Sn合金涂层部分露出的方式连续或不连续地使用，可以抑制Sn或Sn合金涂层中的晶须的产生 形成在其他构件被压焊的基板的表面上，或者形成在待焊接的接合面上。 连续地或不连续地以规定的金属包覆Sn或Sn合金涂层以使得涂层部分露出的方式通过压焊中的接触压力抑制晶须的产生，并且进一步抑制晶须的产生而不损害焊料润湿性 涂层即使当包覆层没有经过热处理或回流时也是如此。

公开(公告)号：US08819933B2

公开(公告)日：2014-09-02

申请号：US12957431

申请日：2010-12-01

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H01R43/02

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种形成电结构的方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。

公开(公告)号：US08591638B2

公开(公告)日：2013-11-26

申请号：US12586464

申请日：2009-09-22

Applicant: Yutaka Morii

Inventor： Yutaka Morii

IPC: C23C22/05 ,  C23C22/48 ,  C23C22/00

CPC classification number: C09D7/1233 ,  C09D7/63 ,  C23C18/48 ,  C23C22/58 ,  C25D3/32 ,  C25D3/60 ,  H01L21/4835 ,  H05K3/22 ,  H05K3/244 ,  H05K3/3473 ,  H05K2201/0769 ,  H05K2203/0789 ,  H05K2203/122

Abstract: A tin or tin alloy plating film surface treatment aqueous solution that can reduce whiskers on the surface of a tin or tin alloy plating film, and can provide a favorable tin or tin alloy plating film using a simple method for tin or tin alloy plating films that are used on electronic components.

公开(公告)号：US08450931B2

公开(公告)日：2013-05-28

申请号：US11883992

申请日：2006-05-09

Applicant: Khristopher Edward Alvarez ,  Nick Evan Shephard ,  James Steven Tonge

Inventor： Khristopher Edward Alvarez ,  Nick Evan Shephard ,  James Steven Tonge

IPC: H01J17/49

CPC classification number: C09D5/086 ,  H01J9/02 ,  H01J11/10 ,  H01J11/22 ,  H01J2211/225 ,  H01L21/76838 ,  H05K3/285 ,  H05K3/323 ,  H05K2201/0769 ,  H05K2203/124

Abstract: A process for reducing Ag electromigration in electronic circuitry includes the step of treating the electronic circuitry with an electromigration resistant composition. This process is useful in fabricating electronic devices having electronic circuitry that is close together, such as resistors, capacitors, and displays, e.g., a plasma display panel (PDP) or a liquid crystal display (LCD).

Abstract translation: 用于减少电子电路中的Ag电迁移的方法包括用电迁移组合物处理电子电路的步骤。 该方法在制造具有诸如电阻器，电容器和显示器（例如等离子体显示面板（PDP）或液晶显示器（LCD））之类的紧密结合的电子电路的电子设备中是有用的。

公开(公告)号：US08212151B2

公开(公告)日：2012-07-03

申请号：US12471802

申请日：2009-05-26

Applicant: Takayuki Yamamoto

Inventor： Takayuki Yamamoto

IPC: H05K1/00

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73203 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H05K1/0254 ,  H05K3/285 ,  H05K3/3436 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/0769 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A wiring substrate includes: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein the plurality of layers contain fillers of different grain diameters, a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, and a grain diameter of the filler contained in the innermost layer is smaller than a shortest interval between adjacent lines of the wiring.

Abstract translation: 布线基板包括：绝缘层; 形成在绝缘层上的布线; 以及形成在所述绝缘层上以便覆盖所述布线的至少一部分的阻焊层，所述阻焊层由多层构成，其中所述多层包含不同晶粒直径的填料，层厚度 用于构成多个层的最内层比布线的层厚度厚，并且包含在最内层中的填料的粒径小于布线的相邻线之间的最短间隔。

公开(公告)号：US08143532B2

公开(公告)日：2012-03-27

申请号：US12366017

申请日：2009-02-05

Applicant: Leilei Zhang

Inventor： Leilei Zhang

IPC: H05K1/11

CPC classification number: H05K3/42 ,  H05K1/0366 ,  H05K3/0055 ,  H05K3/16 ,  H05K3/4076 ,  H05K2201/0769 ,  H05K2201/09581 ,  H05K2201/09827

Abstract: A through hole is formed in a circuit board that has fibers dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating over the sputtered copper layer.

Abstract translation: 在具有分散在聚合物基质中的纤维的电路板中形成通孔。 在通孔内溅射铜，以在溅射的铜层上形成用于电解电镀的足够导电的层。