公开(公告)号：US20130153271A1

公开(公告)日：2013-06-20

申请号：US13764931

申请日：2013-02-12

申请人： Shinko Electric Industries Co., Ltd.

发明人： Michiro Ogawa ,  Kazuhiro Kobayashi ,  Kentaro Kaneko

IPC分类号： H05K1/11 ,  H05K1/09 ,  H05K1/03

CPC分类号： H05K3/188 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/113 ,  H05K3/205 ,  H05K3/244 ,  H05K3/282 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2203/0361 ,  Y10T29/4916 ,  Y10T156/10 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring board includes a pad exposed from an opening portion of an outermost insulating layer. The pad includes: a first metal layer a surface of which is exposed from the wiring board; a second metal layer provided on the first metal layer and formed of a material effective in preventing a metal contained in a via inside the board from diffusing into the first metal layer; and a third metal layer provided between the second metal layer and the via, and formed of a material harder to be oxidized than that of the second metal layer. The thickness of the third metal layer is relatively thick, and is preferably selected to be three times or greater than a thickness of the second metal layer. A side surface of the third metal layer and a surface of the third metal layer to which the via is to be connected are roughed.

公开(公告)号：US08261436B2

公开(公告)日：2012-09-11

申请号：US12646384

申请日：2009-12-23

申请人： Chen-Yueh Kung

发明人： Chen-Yueh Kung

IPC分类号： H01R9/00 ,  H05K3/00

CPC分类号： H05K3/4007 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/0361 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1152 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： A circuit substrate fabricating process includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block. In addition, a fabricating process for the circuit substrate is also provided.

摘要翻译： 电路基板制造工艺包括基底层，图案化导电层，电介质层，外垫和导电块。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 外垫设置在电介质层上。 导电层通过电介质层并连接在外焊盘和内焊盘之间，其中外焊盘和导电块形成为整体单元，外焊盘的外径基本上等于外焊盘 的导电块。 此外，还提供了用于电路基板的制造工艺。

公开(公告)号：US08124880B2

公开(公告)日：2012-02-28

申请号：US11976207

申请日：2007-10-22

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC分类号： H05K1/03

CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

摘要： A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

摘要翻译： 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20110236714A1

公开(公告)日：2011-09-29

申请号：US13123127

申请日：2009-10-13

申请人： Shigeo Ohsaka ,  Toshio Kurosawa ,  Takashi Natsume

发明人： Shigeo Ohsaka ,  Toshio Kurosawa ,  Takashi Natsume

IPC分类号： B32B15/01 ,  C23C14/34 ,  C23C14/14

CPC分类号： C23C14/04 ,  C23C14/044 ,  C23C14/08 ,  C23C14/165 ,  C23C14/542 ,  C23C14/562 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  Y10T428/12493

摘要： A copper foil with an electric resistance film in which a film with higher electrical resistivity than the metal foil is provided on the metal foil, wherein a plurality of electric resistance films with different electric resistance is arranged in parallel on the same metal foil. With conventionally used built-in resistor elements, one resistor element is configured of one type of substance on the copper foil. Nevertheless, when actually mounting the resistor elements, the circuit design tolerance can be increased and the number of man-hours can be reduced with two resistor elements and further with a plurality of resistor elements compared to a case with one resistor element. This invention aims to provide a metal foil with a built-in resistor element comprising two or more types of resistor elements on one metal foil.

摘要翻译： 在金属箔上设置有具有电阻率高于金属箔的膜的具有电阻膜的铜箔，其中在同一金属箔上平行布置具有不同电阻的多个电阻膜。 使用传统使用的内置电阻元件，一个电阻元件由铜箔上的一种物质构成。 然而，当实际安装电阻元件时，与一个电阻器元件相比，可以增加电路设计容差并且可以使用两个电阻元件减少工作时间，并且还可以减少多个电阻元件。 本发明的目的是提供一种具有内置电阻元件的金属箔，该金属箔在一个金属箔上包括两种或多种类型的电阻元件。

公开(公告)号：US20110232951A1

公开(公告)日：2011-09-29

申请号：US13070094

申请日：2011-03-23

申请人： Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

发明人： Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

IPC分类号： H05K1/09

CPC分类号： H05K3/244 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/099 ,  H05K2203/0361 ,  H01L2924/00

摘要： In a wiring laminate portion of a multilayer wiring substrate, a solder resist layer having a plurality of openings is disposed on a main surface side of the laminate structure, and connection terminals are embedded in an outermost resin insulation layer in contact with the solder resist layer. Each of the connection terminals comprises a copper layer and a metallic layer formed of at least one type of metal other than copper. A main-surface-side circumferential portion of the copper layer is covered by the solder resist layer. At least a portion of the metallic layer is located in a recess in a main-surface-side central portion of the copper layer. At least a portion of the metallic layer is exposed via a corresponding opening.

摘要翻译： 在多层布线基板的布线层叠部分中，具有多个开口的阻焊层设置在层叠结构的主表面侧，并且连接端子嵌入在与阻焊层接触的最外层树脂绝缘层中 。 每个连接端子包括铜层和由铜以外的至少一种类型的金属形成的金属层。 铜层的主表面侧圆周部分被阻焊层覆盖。 金属层的至少一部分位于铜层的主表面侧中央部的凹部中。 金属层的至少一部分经由相应的开口露出。

公开(公告)号：US20110108313A1

公开(公告)日：2011-05-12

申请号：US12646384

申请日：2009-12-23

申请人： Chen-Yueh Kung

发明人： Chen-Yueh Kung

IPC分类号： H05K1/11 ,  B44C1/22

CPC分类号： H05K3/4007 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/0361 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1152 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： A circuit substrate includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block. In addition, a fabricating process for the circuit substrate is also provided.

摘要翻译： 电路基板包括基底层，图案化导电层，电介质层，外部焊盘和导电块。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 外垫设置在电介质层上。 导电层通过电介质层并连接在外焊盘和内焊盘之间，其中外焊盘和导电块形成为整体单元，外焊盘的外径基本上等于外焊盘 的导电块。 此外，还提供了用于电路基板的制造工艺。

公开(公告)号：US20100230142A1

公开(公告)日：2010-09-16

申请号：US12739369

申请日：2008-10-23

申请人： Keita Bamba ,  Tadahiro Yokozawa ,  Hideaki Watanabe

发明人： Keita Bamba ,  Tadahiro Yokozawa ,  Hideaki Watanabe

IPC分类号： H05K1/03 ,  B32B38/10

CPC分类号： H05K3/0055 ,  H05K3/025 ,  H05K3/421 ,  H05K3/427 ,  H05K2203/025 ,  H05K2203/0361 ,  H05K2203/1383 ,  H05K2203/1388

摘要： Disclosed is a method for producing a printed wiring board having high dimensional stability with high productivity. The production method comprising the steps of: providing a metal laminate in which a metal layer having an inner metal layer portion and a protection layer portion is laminated on at least one side of an insulating resin layer in such a manner that the inner metal layer portion is arranged on the side of the insulating resin layer; forming a via hole on the metal layer and the insulating resin layer; performing blast processing after forming the via hole; and removing the protection layer portion after performing blast processing.

摘要翻译： 公开了一种生产高尺寸稳定性的印刷线路板的制造方法。 该制造方法包括以下步骤：提供一种金属层压体，其中具有内金属层部分和保护层部分的金属层层压在绝缘树脂层的至少一侧上，使得内金属层部分 布置在绝缘树脂层的侧面上; 在金属层和绝缘树脂层上形成通孔; 在形成通孔之后执行鼓风处理; 并且在执行喷射处理之后去除保护层部分。

公开(公告)号：US20100218978A1

公开(公告)日：2010-09-02

申请号：US12766002

申请日：2010-04-23

申请人： David W. Caldwell ,  Michael Jon Taylor ,  Michael L. Marshall

发明人： David W. Caldwell ,  Michael Jon Taylor ,  Michael L. Marshall

IPC分类号： H05K1/00 ,  H05K3/02

CPC分类号： C23C14/562 ,  G06F2203/04113 ,  H01L31/0232 ,  H05K1/02 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/24 ,  H05K2201/0108 ,  H05K2201/0326 ,  H05K2203/0361 ,  H05K2203/1545 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A layer of transparent conductive material is disposed on a surface of a substrate. Further layers of conductive material are deposited on the layer of transparent conductive material or on an opposite surface of the substrate. The layers are selectively etched to yield a layout of pads for mounting electrical components and conductive traces forming an electrical circuit.

摘要翻译： 透明导电材料层设置在基板的表面上。 另外的导电材料层沉积在透明导电材料层上或衬底的相对表面上。 选择性地蚀刻这些层以产生用于安装电气部件和形成电路的导电迹线的焊盘的布局。

公开(公告)号：US20100193466A1

公开(公告)日：2010-08-05

申请号：US12411219

申请日：2009-03-25

申请人： Chih-Shueh Shih ,  Chao-Hung Lo ,  Jen-Hui Hsu

发明人： Chih-Shueh Shih ,  Chao-Hung Lo ,  Jen-Hui Hsu

IPC分类号： C23F1/00 ,  B05D5/12 ,  C23C14/34 ,  C25D5/34

CPC分类号： H05K3/427 ,  H05K2201/09563 ,  H05K2203/0361 ,  H05K2203/0384

摘要： A method of manufacturing a circuit board is provided. Firstly, a substrate is provided, and a first conductive layer is disposed on the substrate. Next, a barrier layer is formed on the first conductive layer. Thereafter, a through hole passing through the substrate, the first conductive layer, and the barrier layer is formed. A second conductive layer including a conductive rod disposed in the through hole is formed on an inside wall of the through hole and the barrier layer. After that, parts of the second conductive layer located outside the through hole are removed. Next, the barrier layer is removed, and a circuit layer is formed on the first conductive layer and the conductive rod. Parts of the first conductive layer exposed by the circuit layer are then removed.

摘要翻译： 提供一种制造电路板的方法。 首先，设置基板，在基板上设置第一导电层。 接下来，在第一导电层上形成阻挡层。 此后，形成通过基板，第一导电层和阻挡层的通孔。 包括设置在通孔中的导电棒的第二导电层形成在通孔和阻挡层的内壁上。 之后，去除位于通孔外侧的第二导电层的部分。 接下来，去除阻挡层，并且在第一导电层和导电棒上形成电路层。 然后去除由电路层露出的第一导电层的部分。

公开(公告)号：US07698813B2

公开(公告)日：2010-04-20

申请号：US11642660

申请日：2006-12-21

申请人： Te-Chun Wang

发明人： Te-Chun Wang

IPC分类号： H01K3/10

CPC分类号： H05K3/421 ,  C23C18/1603 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/38 ,  C25D5/02 ,  C25D5/34 ,  H05K3/027 ,  H05K2203/0353 ,  H05K2203/0361 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T29/49165

摘要： A method for fabricating a conductive blind via of a circuit substrate including the following steps is provided. First, the circuit substrate including a first dielectric layer, a patterned circuit layer and a second dielectric layer are provided. The patterned circuit layer including at least a capture pad is disposed between the first dielectric layer and the second dielectric layer. Next, a blind via exposing the capture pad is formed in the second dielectric layer. Then, an electroless plating process is performed to form an electroless copper layer on the capture pad and an inner wall of the blind via. Next, the electroless copper layer on the capture pad is removed. Finally, the blind via is filled with a conductive material to form the conductive blind via.

摘要翻译： 提供一种用于制造包括以下步骤的电路基板的导电盲孔的方法。 首先，提供包括第一电介质层，图案化电路层和第二电介质层的电路基板。 至少包括捕获垫的图案化电路层设置在第一介电层和第二电介质层之间。 接下来，在第二电介质层中形成通过曝光捕获垫的盲目。 然后，进行化学镀处理，以在捕获垫上形成化学镀铜层和盲孔的内壁。 接下来，去除捕获垫上的化学镀铜层。 最后，盲孔通过导电材料填充以形成导电盲孔。