公开(公告)号：US08334170B2

公开(公告)日：2012-12-18

申请号：US12163464

申请日：2008-06-27

申请人： Dean Wang ,  Chien-Hsiun Lee ,  Chen-Shien Chen ,  Clinton Chao ,  Mirng-Ji Lii ,  Tjandra Winata Karta

发明人： Dean Wang ,  Chien-Hsiun Lee ,  Chen-Shien Chen ,  Clinton Chao ,  Mirng-Ji Lii ,  Tjandra Winata Karta

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/49811 ,  H01L23/481 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8321 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83986 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.

摘要翻译： 提供了一种用于制造半导体器件的方法，其包括提供第一器件，第二器件和第三器件，在第一器件和第二器件之间提供第一涂层材料，第一涂层材料是未固化的，提供第二涂层 第二装置和第三装置之间的材料，第二涂料未固化，然后以相同的方法固化第一和第二涂料。

公开(公告)号：US20120119354A1

公开(公告)日：2012-05-17

申请号：US12944453

申请日：2010-11-11

申请人： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Ming-Song Sheu ,  Yu-Ling Tsai ,  Chen-Shien Chen ,  Han-Ping Pu

发明人： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Ming-Song Sheu ,  Yu-Ling Tsai ,  Chen-Shien Chen ,  Han-Ping Pu

IPC分类号： H01L23/498 ,  H01L21/50 ,  H01L23/48

CPC分类号： H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/563 ,  H01L23/295 ,  H01L23/562 ,  H01L24/32 ,  H01L24/743 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81191 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/10156 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/10155 ,  H01L2924/00

摘要： A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.

摘要翻译： 模具具有第一表面，与第一表面相对的第二表面，并且侧壁包括第一部分和第二部分，其中第一部分比第二部分更靠近第一表面。 圆角接触模具的侧壁的第一部分并且环绕模具。 工件通过焊料凸块与模具结合，第二表面面向工件。 第一底部填充物填充模具和工件之间的间隙，其中第一底部填充物接触圆角，并且其中第一底部填充物和圆角由不同的材料形成。

公开(公告)号：US08101499B2

公开(公告)日：2012-01-24

申请号：US12751512

申请日：2010-03-31

申请人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

发明人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC分类号： H01L21/30

摘要： An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.

公开(公告)号：US08049323B2

公开(公告)日：2011-11-01

申请号：US11675984

申请日：2007-02-16

申请人： Chen-Shien Chen ,  Chao-Hsiang Yang ,  Jimmy Liang ,  Han-Liang Tseng ,  Mirng-Ji Lii ,  Tjandra Winata Karta ,  Hua-Shu Wu

发明人： Chen-Shien Chen ,  Chao-Hsiang Yang ,  Jimmy Liang ,  Han-Liang Tseng ,  Mirng-Ji Lii ,  Tjandra Winata Karta ,  Hua-Shu Wu

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92244 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19107

摘要： A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.

摘要翻译： 由硅，玻璃，其它陶瓷或其它合适材料形成的芯片保持架包括用于保持半导体芯片的多个凹槽。 半导体芯片的接合焊盘形成在芯片保持器的围绕半导体芯片的区域上或上方，从而扩大接合面积。 使用半导体晶片处理技术将接合焊盘连接到直接形成在半导体芯片上的内部接合焊盘。

公开(公告)号：US20100279463A1

公开(公告)日：2010-11-04

申请号：US12700929

申请日：2010-02-05

申请人： C. W. Hsiao ,  Bo-l Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

发明人： C. W. Hsiao ,  Bo-l Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

IPC分类号： H01L21/78 ,  H01L21/768 ,  H01L21/50 ,  H01L21/56

CPC分类号： H01L23/3114 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/00

摘要： A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

摘要翻译： 公开了一种形成堆叠的模具结构的方法。 多个管芯分别与晶片的第一表面上的多个半导体芯片接合。 在多个管芯和晶片的第一表面上形成封装结构。 封装结构覆盖晶片的第一表面的中心部分并且使晶片的边缘部分露出。 在晶片的边缘部分的第一表面上形成保护材料。

公开(公告)号：US20100117201A1

公开(公告)日：2010-05-13

申请号：US12616562

申请日：2009-11-11

申请人： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming-Hong Tseng ,  Chen-Shien Chen

发明人： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming-Hong Tseng ,  Chen-Shien Chen

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

摘要翻译： 集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。 多个通道被配置成允许流体流过。

公开(公告)号：US20100090319A1

公开(公告)日：2010-04-15

申请号：US12347742

申请日：2008-12-31

申请人： Kuo-Ching Hsu ,  Chen-Shien Chen ,  Hon-Lin Huang

发明人： Kuo-Ching Hsu ,  Chen-Shien Chen ,  Hon-Lin Huang

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/481 ,  H01L24/05 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

摘要： An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.

摘要翻译： 集成电路结构包括具有正面和背面的半导体衬底。 穿透硅通孔（TSV）穿透半导体衬底，其中TSV具有延伸到半导体衬底背面的后端。 再分配线（RDL）形成在半导体衬底的背面上并连接到TSV的后端。 钝化层在RDL上方，其中在钝化层中形成有开口，其中RDL的顶表面的一部分和RDL的侧壁通过开口露出。 在开口处形成金属表面，并与RDL的顶表面和侧壁的部分接触。

公开(公告)号：US20090321948A1

公开(公告)日：2009-12-31

申请号：US12163464

申请日：2008-06-27

申请人： Dean Wang ,  Chien-Hsiun Lee ,  Chen-Shien Chen ,  Clinton Chao ,  Mirng-Ji Lii ,  Tjandra Winata Karta

发明人： Dean Wang ,  Chien-Hsiun Lee ,  Chen-Shien Chen ,  Clinton Chao ,  Mirng-Ji Lii ,  Tjandra Winata Karta

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/49811 ,  H01L23/481 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8321 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83986 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.

摘要翻译： 提供了一种用于制造半导体器件的方法，其包括提供第一器件，第二器件和第三器件，在第一器件和第二器件之间提供第一涂层材料，第一涂层材料是未固化的，提供第二涂层 第二装置和第三装置之间的材料，第二涂料未固化，然后以相同的方法固化第一和第二涂料。

公开(公告)号：US07118451B2

公开(公告)日：2006-10-10

申请号：US10788702

申请日：2004-02-27

申请人： Chen-Shien Chen ,  Yai-Yei Huang ,  Ming-Hsiang Kao ,  Yih-Shung Lin ,  Winata Karta Tjandra

发明人： Chen-Shien Chen ,  Yai-Yei Huang ,  Ming-Hsiang Kao ,  Yih-Shung Lin ,  Winata Karta Tjandra

IPC分类号： B24B49/00

CPC分类号： B24B21/04 ,  B24B37/345 ,  B24B49/02

摘要： A CMP apparatus and process sequence. The CMP apparatus includes multiple polishing pads or belts and an in-line metrology tool which is interposed between adjacent polishing pads or belts in the apparatus. A material layer on each of multiple wafers is successively polished on the polishing pads or belts. The metrology tool is used to measure the thickness of a material layer being polished on each of successive wafers in a lot prior to the final polishing step, in order to precisely polish the layer to a desired target thickness at the final polishing step. This renders unnecessary an additional process cycle to polish the layer on each wafer to the desired target thickness. The metrology tool may be modularized as a unit with the polishing pads or belts.

摘要翻译： CMP装置和处理顺序。 CMP装置包括多个抛光垫或带以及插入在装置中的相邻抛光垫或带之间的在线计量工具。 在多个晶片的每一个上的材料层在抛光垫或带上连续抛光。 测量工具用于测量在最终抛光步骤之前在批次中的每个连续晶片上抛光的材料层的厚度，以便在最终抛光步骤中将层精确抛光到所需目标厚度。 这使得不需要额外的处理循环来将每个晶片上的层抛光到期望的目标厚度。 测量工具可以模块化为具有抛光垫或带的单元。

公开(公告)号：US09613917B2

公开(公告)日：2017-04-04

申请号：US13435809

申请日：2012-03-30

申请人： Ching-Wen Hsiao ,  Chen-Shien Chen

发明人： Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L21/50 ,  H01L23/64 ,  H01L23/538 ,  H01L23/14 ,  H01L21/48 ,  H01L25/10 ,  H01L49/02 ,  H01L23/498

CPC分类号： H01L25/105 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/647 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L28/20 ,  H01L28/60 ,  H01L28/90 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

摘要： A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.