公开(公告)号：US08691662B2

公开(公告)日：2014-04-08

申请号：US13827618

申请日：2013-03-14

Applicant: Soitec

Inventor： Carole David ,  Sébastien Kerdiles

IPC: H01L21/46

CPC classification number: H01L21/02 ,  H01L21/76254

Abstract: A method for fabricating a silicon-on-insulator structure includes forming a first oxide layer on a silicon donor substrate, forming a second oxide layer on a supporting substrate, and forming a weakened zone in the donor substrate. The donor substrate is bonded to the supporting substrate by establishing direct contact between the first oxide layer on the silicon donor substrate and the second oxide layer on the supporting substrate and establishing a direct oxide-to-oxide bond therebetween. The donor substrate is split along the weakened zone to form a silicon-on-insulator structure, and the silicon-on-insulator structure is subjected to two successive rapid thermal annealing processes at temperatures T1 and T2, respectively, wherein T1 is less than or equal to T2, T1 is between 1200° C. and 1300° C., T2 is between 1240° C. and 1300° C., and when T1 is below 1240° C., then T2 is above 1240° C.

Abstract translation: 一种用于制造绝缘体上硅结构的方法包括在硅供体衬底上形成第一氧化物层，在支撑衬底上形成第二氧化物层，并在供体衬底中形成弱化区。 施主衬底通过在硅供体衬底上的第一氧化物层和支撑衬底上的第二氧化物层之间建立直接接触并在其间建立直接的氧化物 - 氧化物键而与支撑衬底结合。 施主衬底沿着弱化区分裂以形成绝缘体上硅结构，并且绝缘体上硅结构分别在温度T1和T2进行两次连续的快速热退火处理，其中T1小于或等于 等于T2，T1在1200℃和1300℃之间，T2在1240℃和1300℃之间，当T1低于1240℃时，则T2高于1240℃。

公开(公告)号：US08637995B2

公开(公告)日：2014-01-28

申请号：US13657327

申请日：2012-10-22

Applicant: Soitec ,  Mariam Sadaka

Inventor： Mariam Sadaka

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76254 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/80097 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00

Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.

Abstract translation: 形成半导体器件的方法包括在电绝缘材料层上提供包括半导体材料层的衬底。 第一金属化层形成在半导体材料层的第一侧上。 通过晶片互连件至少部分地通过衬底发泡。 第二金属化层形成在半导体材料层的与其第一侧相对的第二侧上。 提供了一种电路，其通过第一金属化层，衬底和第二金属化层延伸，所述第一金属化层和第二金属化层位于由半导体材料层的第一侧上的衬底承载的第一处理半导体结构和由第 衬底在半导体材料层的第一侧上。 使用这种方法制造半导体结构。

公开(公告)号：US08625374B2

公开(公告)日：2014-01-07

申请号：US13718571

申请日：2012-12-18

Applicant: Soitec

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: G11C7/00 ,  G11C11/4091

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2211/4016

Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

Abstract translation: 一种用于存储器的一系列单元的读出放大器，包括一个写入级，它包括一个CMOS反相器，其输入直接或间接地连接到读出放大器的输入端，并且其输出端连接到输出端 所述读出放大器旨在连接到寻址该串联的单元的本地位线;以及读取级，其包括检测晶体管，其栅极连接到反相器的输出端，其漏极连接到 输入变频器。

公开(公告)号：US20130299997A1

公开(公告)日：2013-11-14

申请号：US13937779

申请日：2013-07-09

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2221/6839 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/05009 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08146 ,  H01L2224/80006 ,  H01L2224/80065 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00

Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.

Abstract translation: 形成键合的半导体结构的方法包括暂时将半导体结构直接结合在一起，使半导体结构中的至少一个变薄，然后将稀化的半导体结构永久地结合到另一个半导体结构。 可以在不使用粘合剂的情况下建立临时的直接粘合。 结合的半导体结构根据这样的方法制造。

公开(公告)号：US20130295708A1

公开(公告)日：2013-11-07

申请号：US13933855

申请日：2013-07-02

Applicant: Soitec

Inventor： Christiaan J. Werkhoven

IPC: H01L21/02

CPC classification number: H01L21/0262 ,  C23C16/301 ,  C23C16/4488 ,  C23C16/45551 ,  C23C16/545 ,  H01L21/02538 ,  H01L21/0254

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Abstract translation: 将III-V族半导体材料沉积在衬底上的方法包括通过相对于多个气体柱改变衬底的空间定位，将III族元素的气态前体和V族元素的气态前体顺序地引入衬底 。 例如，衬底可以相对于多个基本排列的气体柱移动，每个气体柱设置不同的前体。 用于产生前体的热化气体注入器可以包括入口，热化管道，配置成将液体试剂保持在其中的液体容器和出口。 用于在衬底的表面上形成一个或多个III-V半导体材料的沉积系统可以包括一个或多个这样的热化气体注入器，其构造成经由多个气体柱将前体引导到衬底。

公开(公告)号：US20130280892A1

公开(公告)日：2013-10-24

申请号：US13919539

申请日：2013-06-17

Applicant: Soitec

Inventor： Ronald Thomas Bertram, JR.

IPC: H01L21/02

CPC classification number: H01L21/0262 ,  C23C16/301 ,  C23C16/303 ,  C23C16/4488 ,  C23C16/452 ,  C30B25/14 ,  C30B29/403

Abstract: Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors.

Abstract translation: 在衬底上沉积材料的方法包括从热化气体注入器内的源气体形成前体气体和副产物。 副产物可以与液体试剂反应以形成额外的前体气体，其可以从热化气体注入器注入反应室。 用于将气体注入沉积系统的反应室的热化气体注入器可以包括入口，热化管道，配置成将液体试剂保持在其中的液体容器和出口。 通道可以从入口，通过热化管道延伸到液体容器内的内部空间，以及从液体容器内的内部空间延伸到出口。 热化导管的长度可以大于入口和液体容器之间的最短距离。 沉积系统可以包括一个或多个这样的热化气体注入器。

公开(公告)号：US20130256907A1

公开(公告)日：2013-10-03

申请号：US13900157

申请日：2013-05-22

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

公开(公告)号：US20130221496A1

公开(公告)日：2013-08-29

申请号：US13848201

申请日：2013-03-21

Applicant: Soitec

Inventor： Christiaan J. Werkhoven ,  Chantal Arena

IPC: H01L21/762 ,  H01L29/02

CPC classification number: H01L21/76256 ,  H01L21/187 ,  H01L29/02 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/40 ,  H01L2933/0016

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.

Abstract translation: 实施例涉及半导体结构及其形成方法。 在一些实施例中，所述方法可用于通过在预定深度处在供体结构中形成弱化区以制造半导体衬底，以在附着表面和弱化区之间限定转移层，以及在弱化区和弱化区之间的残留施主结构 与附接表面相对的表面。 在附着表面上形成金属层，并且在金属层和转移层之间提供欧姆接触，匹配的金属层的热膨胀系数（CTE）与转印层的CTE紧密匹配，并具有足够的刚度 为转移层提供结构支持。 在弱化区将转移层与供体结构分离，以形成包含转移层金属层的复合衬底。

公开(公告)号：US20130210171A1

公开(公告)日：2013-08-15

申请号：US13838031

申请日：2013-03-15

Applicant: SOITEC

Inventor： Gweltaz Gaudin

IPC: H01L21/18

CPC classification number: H01L21/185 ,  B32B37/144 ,  B32B37/18 ,  B32B38/1808 ,  B32B38/1866 ,  B32B41/00 ,  B32B2041/04 ,  B32B2307/202 ,  B32B2309/72 ,  B32B2457/14 ,  H01L21/187 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/75702 ,  H01L2224/75703 ,  H01L2224/75756 ,  H01L2224/75901 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2924/3511 ,  Y10T156/10 ,  Y10T156/1089 ,  Y10T156/1092 ,  H01L2224/80

Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

Abstract translation: 一种用于通过分子粘合将第一晶片接合在第二晶片上的方法，其中晶片在它们之间具有初始的径向不对准。 该方法包括使两个晶片接触，以便在两个晶片之间启动键合波的传播，同时在接触步骤期间将两个晶片中的至少一个施加预定的接合曲率作为初始径向失准的函数 。

公开(公告)号：US20130137247A1

公开(公告)日：2013-05-30

申请号：US13751558

申请日：2013-01-28

Applicant: Soitec

Inventor： Chantal Arena ,  Christiaan J. Werkhoven ,  Ronald Thomas Bertram, JR. ,  Ed Lindow

IPC: H01L21/02

CPC classification number: H01L21/0262 ,  C23C16/303 ,  C23C16/448 ,  C30B25/105

Abstract: The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.

Abstract translation: 本发明涉及半导体处理领域，并且提供了通过在其反应之前促进前体气体的更有效的热化来改善半导体材料的化学气相沉积（CVD）的方法。 在优选的实施方案中，该方法提供热传递结构及其在CVD反应器内的布置，以便促进对流动的工艺气体的热传递。 在适用于对来自加热灯的辐射透明的CVD反应器的某些优选实施方案中，本发明提供放射吸收表面，其被放置以拦截来自加热灯的辐射并将其转移到流动的工艺气体。