公开(公告)号：US08860229B1

公开(公告)日：2014-10-14

申请号：US13943401

申请日：2013-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00

CPC classification number: H01L24/82 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/80 ,  H01L27/0688 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80855 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/9202 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a polymer material and a second conductive material embedded in a second polymer material. The first conductive material of the first semiconductor wafer bonded to the second conductive material of the second semiconductor wafer and the first polymer material of the first semiconductor wafer is bonded to the second polymer material of the second semiconductor wafer. The semiconductor device structure further includes at least one through substrate via (TSV) extending from a bottom surface of the second semiconductor wafer to a top surface of the first semiconductor wafer.

Abstract translation: 提供了形成半导体器件结构的实施例。 半导体器件结构包括通过混合键合结构接合的第一半导体晶片和第二半导体晶片，并且该混合键合结构包括嵌入聚合物材料中的第一导电材料和嵌入第二聚合物材料中的第二导电材料。 与第二半导体晶片的第二导电材料接合的第一半导体晶片的第一导电材料和第一半导体晶片的第一聚合物材料接合到第二半导体晶片的第二聚合物材料。 半导体器件结构还包括从第二半导体晶片的底表面延伸到第一半导体晶片的顶表面的至少一个贯穿衬底通孔（TSV）。

公开(公告)号：US12131898B2

公开(公告)日：2024-10-29

申请号：US17745182

申请日：2022-05-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L21/02104 ,  H01L21/8221 ,  H01L27/0688 ,  H01L21/2007 ,  H01L21/76254 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided that includes operations as follows: bonding an epitaxial layer formed with a first semiconductor substrate and an ion-implanted layer that is formed between the epitaxial layer and the first semiconductor substrate, to a bonding oxide layer of a second semiconductor substrate; separating the first semiconductor substrate from the epitaxial layer, by removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping the epitaxial layer; and forming a first semiconductor device portion on the epitaxial layer, and an interconnect layer on the first semiconductor device portion.

公开(公告)号：US12057432B2

公开(公告)日：2024-08-06

申请号：US16933593

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/96 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/02205 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/1027 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

公开(公告)号：US20240105632A1

公开(公告)日：2024-03-28

申请号：US18525966

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L24/16 ,  H01L25/0652

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US11854826B2

公开(公告)日：2023-12-26

申请号：US17869150

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L21/321 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/498 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L21/321 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76888 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/5329 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/83005

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

公开(公告)号：US11764139B2

公开(公告)日：2023-09-19

申请号：US17372747

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L21/00 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/01047 ,  H01L2224/05611 ,  H01L2924/01082 ,  H01L2224/81121 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/1144 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.

公开(公告)号：US11527454B2

公开(公告)日：2022-12-13

申请号：US17362185

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Hsin Wei ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Hsien-Pin Hu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L23/16 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L25/03 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

公开(公告)号：US11515288B2

公开(公告)日：2022-11-29

申请号：US16934631

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Tsei-Chung Fu ,  Jing-Cheng Lin

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31

Abstract: A method includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.

公开(公告)号：US20220359223A1

公开(公告)日：2022-11-10

申请号：US17869150

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L21/321 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/768

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

公开(公告)号：US11488882B2

公开(公告)日：2022-11-01

申请号：US16989047

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L23/433 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L21/78 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/60

Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.