公开(公告)号：US20170345578A1

公开(公告)日：2017-11-30

申请号：US15675977

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Fred D. Fishburn

IPC: H01G4/38 ,  H01G4/30

CPC classification number: H01G4/385 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30 ,  H01G4/40 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H01L28/00 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16265 ,  H01L2924/19041 ,  H01L2924/19104 ,  H05K1/162 ,  H05K2201/09763 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

公开(公告)号：US20150264813A1

公开(公告)日：2015-09-17

申请号：US14204898

申请日：2014-03-11

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K1/16 ,  H05K1/11

CPC classification number: H05K1/162 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5223 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4673 ,  H05K2201/0179 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2201/10378

Abstract: A chip-stack interposer structure including a passive device is described, including an interposing layer, a capacitor, a first contact and a second contact. The capacitor is embedded in or disposed on the interposing layer, including a first electrode, a second electrode and a dielectric layer between the first and the second electrodes. The first contact is connected with the first electrode. The second contact is connected with the second electrode. The first electrode and the second electrode are disposed at the same side of the interposing layer or at different sides of the interposing layer.

Abstract translation: 描述包括无源器件的芯片堆叠插入器结构，包括中介层，电容器，第一接触和第二接触。 电容器嵌入或设置在插入层上，包括在第一和第二电极之间的第一电极，第二电极和介电层。 第一触点与第一电极连接。 第二触点与第二电极连接。 第一电极和第二电极设置在插入层的相同侧或者插入层的不同侧。

公开(公告)号：US08698278B2

公开(公告)日：2014-04-15

申请号：US12933522

申请日：2009-03-24

Applicant: Masaki Muramatsu

Inventor： Masaki Muramatsu

IPC: H01L27/08

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/02 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 10 includes a core substrate 11, a first capacitor 301, a wiring laminate portion 31, and a second capacitor 101. An accommodation hole portion 90 of the core substrate 11 accommodates the first capacitor 101 therein, and a component-mounting region 20 is set on a surface 39 of the wiring laminate portion 31. The second capacitor 101 has electrode layers 102, 103 and a dielectric layer 104. The second capacitor 101 is embedded in the wiring laminate portion 31 in such a state that first main surfaces 105, 107 and second main surfaces 106, 108 are in parallel with the surface 39 of the wiring laminate portion 31, and is disposed between the first capacitor 301 and the component-mounting region 20.

Abstract translation: 目的是提供一种能够解决由连接部件和电容器的布线的长度增加引起的问题的配有部件的布线基板。 构成部件的布线基板10具有芯基板11，第一电容器301，布线层叠部31和第二电容器101.芯基板11的容纳孔部90容纳第一电容器101， 安装区域20设置在布线层叠部分31的表面39上。第二电容器101具有电极层102,103和电介质层104.第二电容器101以这样的状态嵌入布线层叠部分31中 第一主表面105,107和第二主表面106,108与布线层压体部分31的表面39平行，并且设置在第一电容器301和部件安装区域20之间。

公开(公告)号：US08564967B2

公开(公告)日：2013-10-22

申请号：US11949329

申请日：2007-12-03

Applicant: Daniel Irwin Amey, Jr. ,  William J. Borland

Inventor： Daniel Irwin Amey, Jr. ,  William J. Borland

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09763 ,  H05K2201/10674

Abstract: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

Abstract translation: 一种印刷线路板半导体封装或PWB功率核，其包括嵌入在所述印刷线路板半导体封装的多层上的单片电容器，其中每个嵌入式电容器的至少一部分位于所述管芯阴影内，并且其中所述嵌入式单片电容器包括至少第一 电极和第二电极。 嵌入式单片电容器的第一电极和第二电极分别与半导体器件的Vcc（功率）端子和Vss（接地）端子互连。 嵌入式电容器的尺寸变化以产生不同的自谐振频率，并且它们在PWB半导体封装内的垂直布置用于控制电容器 - 半导体电互连的固有电感，从而可以实现嵌入式电容器的定制谐振频率 具有低阻抗。

公开(公告)号：US08563420B2

公开(公告)日：2013-10-22

申请号：US13561247

申请日：2012-07-30

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract translation: 一种制造印刷电路板的方法包括在第一金属层上形成含有原料陶瓷材料的未煅烧层，焙烧形成在第一金属层上的未煅烧层，使得具有以片状形式煅烧的陶瓷体的高介电常数层 形成在第一金属层上，相对于第一金属层在高介电常数层的相对侧的高介电常数层上形成第二金属层，使得具有高介电常数层的层状电容器和第一金属层 形成夹着高介电常数层的第二层电极，并将层叠电容器配置在主体中。

公开(公告)号：US08536463B2

公开(公告)日：2013-09-17

申请号：US12923997

申请日：2010-10-20

Applicant: Mitsuharu Shoji ,  Kiwamu Adachi

Inventor： Mitsuharu Shoji ,  Kiwamu Adachi

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/125

Abstract: A method for manufacturing a printed-circuit board including: a capacitive element forming step of embedding a capacitive element in a substrate resin layer inside a substrate that includes a plurality of wiring layers laminated with the substrate resin layer interposed in between, the capacitive element forming step including forming a lower electrode using a conductive layer on one of the plurality of wiring layers, or using one of the plurality of wiring layers; forming a crystalline metal oxide-containing capacitor dielectric film at a temperature at or below a heat-resistant temperature of the substrate resin layer, and at or above room temperature; and forming an upper electrode on an upper surface of the capacitor dielectric film on the side opposite to the lower electrode.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，包括：电容元件形成步骤，将电容元件嵌入到基板内部的基板树脂层内，所述基板包括与介于其间的基板树脂层层叠的多个布线层，所述电容元件形成 包括在所述多个布线层之一上使用导电层形成下电极，或者使用所述多个布线层中的一个布线层; 在等于或低于衬底树脂层的耐热温度或低于室温的温度下形成含结晶金属氧化物的电容器电介质膜; 以及在所述电容器电介质膜的与所述下电极相反的一侧的上表面上形成上电极。

公开(公告)号：US08470680B2

公开(公告)日：2013-06-25

申请号：US12180768

申请日：2008-07-28

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC: H01G4/005

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

公开(公告)号：US20130120902A1

公开(公告)日：2013-05-16

申请号：US13812348

申请日：2011-07-07

Applicant: Hitoshi Noguchi ,  Kenichi Ezaki

Inventor： Hitoshi Noguchi ,  Kenichi Ezaki

IPC: H01G4/232

CPC classification number: H01G4/232 ,  H01G4/12 ,  H01G4/18 ,  H01G4/33 ,  H05K1/162 ,  H05K2201/09609 ,  H05K2201/09763 ,  H05K2203/0338 ,  Y10T29/435

Abstract: A substrate-incorporated capacitor includes a first electrode extending in a predetermined direction, a dielectric layer arranged on the first electrode, a second electrode arranged on the dielectric layer and facing the first electrode through the dielectric layer, wherein the second electrode includes an end projecting from the dielectric layer in the predetermined direction, and an electrode layer spaced apart from the first electrode in the predetermined direction. The end of the second electrode is connected to the electrode layer in the predetermined direction. The electrode layer includes a surface that is flush with a surface of the first electrode.

Abstract translation: 基板合并电容器包括沿预定方向延伸的第一电极，布置在第一电极上的电介质层，布置在电介质层上并通过电介质层面对第一电极的第二电极，其中第二电极包括端部突出 从预定方向上的电介质层和与预定方向上的第一电极隔开的电极层。 第二电极的端部沿预定方向连接到电极层。 电极层包括与第一电极的表面齐平的表面。

公开(公告)号：US08391015B2

公开(公告)日：2013-03-05

申请号：US12357867

申请日：2009-01-22

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K7/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/305 ,  H05K2201/0175 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10977

Abstract: A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer being interposed between a first and a second electrode, and a semiconductor device mounting pad, including a first and a second pad, formed on an outermost resin insulating layer of the resin insulating layers. An underfill which covers an area larger than that of the high dielectric layer is formed, when the underfill covered area is projected along a lamination direction of the resin insulating layers to a face on which the high dielectric layer is formed. The capacitor is located immediately beneath the underfill covered area.

Abstract translation: 一种印刷线路板包括绝缘层和一个电容器，该电容器包括介于第一和第二电极之间的陶瓷高介电层，以及半导体器件安装衬垫，包括第一和第二衬垫，该衬底形成在第一和第二衬底的最外层树脂绝缘层上 树脂绝缘层。 当底层覆盖区域沿着树脂绝缘层的层叠方向突出到形成有高介电层的面时，形成覆盖比高介电层的面积大的面积的底部填充物。 电容器位于底部填充区域的正下方。

公开(公告)号：US20120106032A1

公开(公告)日：2012-05-03

申请号：US13345227

申请日：2012-01-06

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

IPC: H01G9/025 ,  H01G9/04 ,  H01G9/15 ,  H01G7/00

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。