公开(公告)号：US20150136854A1

公开(公告)日：2015-05-21

申请号：US14396463

申请日：2012-05-08

Applicant: Jun Lu ,  Young Liu ,  Xi Tao ,  Feng Chen ,  Ynjiun Paul Wang

Inventor： Jun Lu ,  Young Liu ,  Xi Tao ,  Feng Chen ,  Ynjiun Paul Wang

IPC: G06K7/10

CPC classification number: G06K7/10722 ,  G06K7/10009 ,  G06K7/10851 ,  G06K7/1413 ,  G06K19/06028 ,  H04N5/2251 ,  H04N5/23203 ,  H04N5/353 ,  H04N5/378

Abstract: An encoded information reading (EIR) terminal can comprise a microprocessor communicatively coupled to a system bus, a memory, a communication interface, and a pluggable imaging assembly identified by a type identifier and configured to acquire an image comprising decodable indicia. The imaging assembly can comprise a two-dimensional image sensor configured to output an analog signal representative of the light reflected by an object located within the field of view of the imaging assembly. The EIR terminal can be configured to output, by processing the analog signal, the raw image data derived from the analog signal and/or a decoded message corresponding to the decodable indicia. The imaging assembly can be communicatively coupled to the system bus via an imaging assembly interface comprising a plurality of wires and a multi-pin connector. The imaging assembly inter face can comprise one or more wires configured to carry the imaging assembly type identifier. The EIR terminal can be configured, responsive to receiving the type identifier via the one or more wires, to retrieve from the memory one or more imaging assembly configuration information items corresponding to the type identifier and/or to receive via the communication interface one or more imaging assembly configuration information items corresponding to the type identifier. The EIR terminal can be further configured to control the imaging assembly using the imaging assembly configuration information items.

Abstract translation: 编码信息读取（EIR）终端可以包括通信地耦合到系统总线，存储器，通信接口和由类型标识符标识并被配置为获取包括可解码标记的图像的可插拔成像组件的微处理器。 成像组件可以包括被配置为输出表示由位于成像组件的视场内的物体反射的光的模拟信号的二维图像传感器。 EIR终端可以被配置为通过处理模拟信号来输出从模拟信号导出的原始图像数据和/或对应于可解码标记的解码消息。 成像组件可以经由包括多根电线和多针连接器的成像组件接口通信地耦合到系统总线。 成像组件界面可以包括一个或多个配置成承载成像组件类型标识符的线。 响应于经由一条或多条线路接收到类型标识符，可以配置EIR终端，以从存储器检索与该类型标识符相对应的一个或多个成像组件配置信息项和/或经由通信接口接收一个或多个 对应于类型标识符的成像组件配置信息项。 EIR终端还可以被配置成使用成像组件配置信息项来控制成像组件。

公开(公告)号：US09006870B2

公开(公告)日：2015-04-14

申请号：US13955206

申请日：2013-07-31

Applicant: Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

Inventor： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Abstract translation: 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三个半导体芯片堆叠在餐夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US20150040061A1

公开(公告)日：2015-02-05

申请号：US13997752

申请日：2012-08-24

Applicant: Jun Lu ,  Yipeng Yang ,  Edwin L. Wang

Inventor： Jun Lu ,  Yipeng Yang ,  Edwin L. Wang

IPC: G06F3/0481 ,  G06F3/0484

CPC classification number: G06F3/0481 ,  G06F3/04842 ,  G06F3/1462 ,  G09G5/14 ,  G09G5/42 ,  G09G2370/022

Abstract: A device, method and system of displaying a file on a mobile communication device may comprise duplicating at least a leftmost part of a file to obtain a duplicated leftmost part of the file, and displaying a frame through moving a display window along the frame, the frame comprising a rightmost part of the file and the duplicated leftmost part of the file, wherein the duplicated leftmost part of the file is placed on right of the rightmost part of the file. In some embodiments, the mobile communication device may control the display window to automatically move to a leftmost side of the frame, if the display window moves to a rightmost side of the frame, and further in response to a user instruction of continuing viewing the file.

Abstract translation: 在移动通信设备上显示文件的装置，方法和系统可以包括复制文件的至少最左部分以获得文件的最左边部分，并且通过沿着帧移动显示窗口来显示帧， 所述文件的最右边部分和所述文件的最左边部分是所述文件的最右边部分，所述文件的最左边部分位于所述文件的最右边部分的右侧。 在一些实施例中，如果显示窗口移动到帧的最右侧，则移动通信设备可以控制显示窗口自动移动到帧的最左侧，并且还响应于用户继续观看文件的指令 。

公开(公告)号：US08859508B2

公开(公告)日：2014-10-14

申请号：US12669653

申请日：2008-07-25

Applicant: Jijun Chen ,  Lin Xu ,  Jun Zhou ,  Jun Lu ,  Rongrong Mao ,  Meng Tian ,  Qixin Zhou ,  Xuemei Zhang ,  Yong Shen ,  Zhiyong Jiang ,  Aixue Zuo

Inventor： Jijun Chen ,  Lin Xu ,  Jun Zhou ,  Jun Lu ,  Rongrong Mao ,  Meng Tian ,  Qixin Zhou ,  Xuemei Zhang ,  Yong Shen ,  Zhiyong Jiang ,  Aixue Zuo

IPC: A61K31/70 ,  A61K31/05 ,  A23L1/30 ,  A61K31/7032 ,  C07H15/203

CPC classification number: A23L1/30 ,  A23L33/10 ,  A23L33/105 ,  A61K31/05 ,  A61K31/7032 ,  C07H15/203

Abstract: The present invention relates to the application of 5-methyl-1,3-benzenediol or its derivatives represented by Formula I; wherein the constituent variables are as defined herein or pharmaceutical compositions thereof containing them in the preparation of medicines or functional foods. The present studies indicate that 5-methyl-1,3-benzenediol or its derivatives represented by Formula I, wherein the constituent variables are as defined herein or pharmaceutical compositions thereof containing them show more significant antidepressant effects than fluoxetine or imipramine.

Abstract translation: 本发明涉及式I表示的5-甲基-1,3-苯二酚或其衍生物的应用; 其中组分变量如本文所定义，或其药物组合物含有它们在制备药物或功能性食品中。 本研究表明，式I表示的5-甲基-1,3-苯二酚或其衍生物，其中组分变量如本文所定义，或含有它们的药物组合物显示比氟西汀或丙咪嗪更显着的抗抑郁作用。

公开(公告)号：US20140264802A1

公开(公告)日：2014-09-18

申请号：US13797440

申请日：2013-03-12

Applicant: Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

Inventor： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

IPC: H01L23/495 ,  H01L21/58

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L21/566 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/03

Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Abstract translation: 具有厚底部金属的半导体器件包括在其前表面覆盖有顶部塑料封装层的半导体芯片和在其后表面处的背面金属层，顶部塑料封装层围绕金属凸块的侧壁与金属的顶表面 从顶部塑料封装层暴露的凸起，用于半导体芯片的芯片安装在其上以及塑料封装主体。

公开(公告)号：US08709893B2

公开(公告)日：2014-04-29

申请号：US13216122

申请日：2011-08-23

Applicant: Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

Inventor： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

IPC: H01L29/78

CPC classification number: H01L29/7811 ,  H01L21/30604 ,  H01L21/30608 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/8309 ,  H01L2224/83141 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

Abstract translation: 本发明涉及功率半导体器件及其制备方法。 特别地，本发明旨在提供一种降低功率MOSFET的Rdson（漏源电阻）的基板贡献的方法以及通过该方法制造的功率MOSFET器件。 通过在Si衬底的底部形成一个或多个底部沟槽，有效地降低归因于衬底的功率MOSFET器件的导通电阻。 与具有底槽的衬底互补的匹配引线框架底座进一步改善了功率MOSFET器件的封装。

公开(公告)号：US08669650B2

公开(公告)日：2014-03-11

申请号：US13244256

申请日：2011-09-23

Applicant: Xiaotian Zhang ,  Hamza Yilmaz ,  Jun Lu ,  Xiaoguang Zeng ,  Ming-Chen Lu

Inventor： Xiaotian Zhang ,  Hamza Yilmaz ,  Jun Lu ,  Xiaoguang Zeng ,  Ming-Chen Lu

IPC: H01L23/495 ,  H01L23/02

CPC classification number: H01L23/49524 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/84 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40135 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.

Abstract translation: 一种半导体器件封装，包括具有包括第一芯片安装区域和第二芯片安装区域的模板的引线框架，形成在第一芯片安装区域中的凹部区域和形成在凹部区域中的多个金属柱，凹口将 第一芯片安装区域横向延伸的横向基部和纵向延伸的纵向基部，并且将凹部区域分离成形成在横向基部中的横向凹部和形成在纵向基部中的纵向凹部; 连接到外部销的横向延伸部分的一部分延伸到凹口内部的一部分。

公开(公告)号：US08586414B2

公开(公告)日：2013-11-19

申请号：US12968159

申请日：2010-12-14

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Anup Bhalla ,  Jun Lu ,  Kal Liu

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Anup Bhalla ,  Jun Lu ,  Kal Liu

IPC: H01L21/00

CPC classification number: H01L23/49562 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

Abstract translation: 半导体封装及其制造方法包括具有管芯焊盘的引线框架和设置在顶表面上的大致V形槽的源极引线。 设置在芯片焊盘上的半导体芯片。 连接到芯片的顶表面电极的金属板具有在V沟槽中终止的弯曲延伸部，与V沟槽侧壁中的至少一个接触。

公开(公告)号：US08513784B2

公开(公告)日：2013-08-20

申请号：US12726892

申请日：2010-03-18

Applicant: Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

Inventor： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73263 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

Abstract translation: 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。

公开(公告)号：US20130210195A1

公开(公告)日：2013-08-15

申请号：US13547358

申请日：2012-07-12

Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC: H01L21/78

CPC classification number: H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

Abstract translation: WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。