公开(公告)号：US08759150B2

公开(公告)日：2014-06-24

申请号：US13488188

申请日：2012-06-04

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC: H01L21/50

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

Abstract translation: 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

公开(公告)号：US20140035135A1

公开(公告)日：2014-02-06

申请号：US13572302

申请日：2012-08-10

Applicant: Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract translation: 用于球栅阵列（BGA）的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属（UBM）层和焊料凸块。 焊料凸块具有凸块宽度和凸块高度，并且凸块高度比凸块宽度的比值小于1。

公开(公告)号：US20140011301A1

公开(公告)日：2014-01-09

申请号：US13542896

申请日：2012-07-06

Applicant: Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

Inventor： Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

IPC: H01L21/66 ,  G06F19/00

CPC classification number: H01L22/20 ,  H01L21/76898 ,  H01L22/12

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.

Abstract translation: 本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤识别动作。

公开(公告)号：US20130285244A1

公开(公告)日：2013-10-31

申请号：US13457841

申请日：2012-04-27

Applicant: Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Wen-Chih Chiou ,  Yen-Hung Chen ,  Sylvia Lo ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L21/76898 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552

Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.

Abstract translation: 公开了一种用于向TSV提供沉积在TSV的顶表面下方的阻挡层的系统和方法，顶表面具有减小的地形变化。 将底部TSV焊盘沉积到通孔中，然后抛光，使得顶表面在衬底顶表面下方。 然后在通孔中沉积阻挡层，并且沉积在阻挡层上的顶部TSV焊盘。 顶部的TSV屏障垫被抛光，以使顶部TSV焊盘的顶部表面与衬底的高度一致。 阻挡垫可以小于约1微米厚，并且顶部TSV垫可以小于约6微米厚。 阻挡垫可以是来自顶部和底部TSV垫的不同金属，并且可以选自包括钛，钽，钴，镍等的组。

公开(公告)号：US08536573B2

公开(公告)日：2013-09-17

申请号：US13310448

申请日：2011-12-02

Applicant: Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/58 ,  H01L23/48

CPC classification number: H01L22/32 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/11464 ,  H01L2224/11825 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2224/05552

Abstract: A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.

Abstract translation: 提供了一种用于电镀连接到测试垫的触点的系统和方法。 一个实施例包括将阻塞材料插入到接触件和测试垫之间的通孔中。 在另一个实施例中，阻挡结构可以插入在接触件和测试垫之间。 在另一个实施例中，阻挡层可以插入到触点叠层中。 一旦已经形成了阻挡材料，阻挡结构或阻挡层，则可以用阻挡材料，阻挡结构或阻挡层电镀接触，从而降低或防止由于电偶效应导致的测试焊盘的劣化。

公开(公告)号：US08518753B2

公开(公告)日：2013-08-27

申请号：US13296922

申请日：2011-11-15

Applicant: Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/00

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate.

Abstract translation: 一种方法包括将插入件的第一侧附着在载体晶片上。 插入器的第一侧包括多个凸块。 载体晶片包括形成在载体晶片中的多个空腔。 插入器的第一侧上的每个凸块可以装配到载体晶片上的相应空腔中。 随后，该方法包括在插入器的第二侧上附加半导体管芯以形成晶片堆叠，将晶片堆叠与载体晶片分离并将晶片堆叠连接到基板。

公开(公告)号：US20130217188A1

公开(公告)日：2013-08-22

申请号：US13398672

申请日：2012-02-16

Applicant: Chung Yu Wang ,  Shih-Yi Syu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Shih-Yi Syu ,  Jing-Cheng Lin

IPC: H01L21/50 ,  H01L21/78 ,  H01L23/48

CPC classification number: H01L23/433 ,  H01L21/563 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.

Abstract translation: 一种装置包括一个封装部件和一个模具，并结合到封装部件上。 芯片包括基板。 散热器通过直接接合设置在基板的背面上并结合到基板的背面。

公开(公告)号：US20130140563A1

公开(公告)日：2013-06-06

申请号：US13310448

申请日：2011-12-02

Applicant: Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/522

CPC classification number: H01L22/32 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/11464 ,  H01L2224/11825 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2224/05552

Abstract: A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.

公开(公告)号：US08426961B2

公开(公告)日：2013-04-23

申请号：US12823851

申请日：2010-06-25

Applicant: Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L21/76885 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4007 ,  H05K2203/016 ,  H05K2203/025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/16145 ,  H01L2924/00012

Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

Abstract translation: 一种装置包括：插入件，其包括基板; 以及衬底上的至少一个电介质层。 多个穿通基板通孔（TSV）穿透基板。 第一金属凸块在至少一个电介质层中并电耦合到多个TSV。 第二金属凸块在至少一个电介质层的上方。 模具嵌入在至少一个电介质层中并结合到第一金属凸块。

公开(公告)号：US08411459B2

公开(公告)日：2013-04-02

申请号：US12834943

申请日：2010-07-13

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H05K7/00 ,  H05K1/16

CPC classification number: H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15321 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A device includes an interposer including a substrate, and a first through-substrate via (TSV) penetrating through the substrate. A glass substrate is bonded to the interposer through a fusion bonding. The glass substrate includes a second TSV therein and electrically coupled to the first TSV.

Abstract translation: 一种器件包括内插器，其包括衬底和穿透衬底的第一穿透衬底通孔（TSV）。 玻璃基板通过熔接结合到插入件上。 玻璃基板在其中包括第二TSV并且电耦合到第一TSV。