公开(公告)号：US20180069052A1

公开(公告)日：2018-03-08

申请号：US15803732

申请日：2017-11-03

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L27/22

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.

公开(公告)号：US20170133432A1

公开(公告)日：2017-05-11

申请号：US15409740

申请日：2017-01-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/24 ,  H01L29/66 ,  H01L29/167 ,  H01L29/78 ,  H01L45/00 ,  H01L29/04

CPC classification number: H01L27/2436 ,  G11C13/0021 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2236 ,  H01L21/31116 ,  H01L21/324 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L29/04 ,  H01L29/167 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

公开(公告)号：US20160343774A1

公开(公告)日：2016-11-24

申请号：US15224929

申请日：2016-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一存储单元; 第二存储单元，包括第二晶体管，其中所述第二晶体管覆盖所述第一晶体管，所述第二晶体管与所述第一晶体管自对准; 以及多个无连接晶体管，其中至少一个无连接晶体管控制对至少一个存储单元的访问。

公开(公告)号：US09385088B2

公开(公告)日：2016-07-05

申请号：US14626563

申请日：2015-02-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/538 ,  H01L45/00 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11 ,  H01L27/06 ,  H01L27/088 ,  H01L27/085 ,  H01L27/092 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L23/5386 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一层，所述第一晶体管包括至少一个第一单晶硅晶体管沟道; 第二层，包括包括至少一个第二单晶非硅晶体管沟道的第二晶体管; 从第二晶体管延伸到第一晶体管的多个连接路径，其中至少一个连接路径包括直径小于200nm的至少一个贯穿层通孔。

公开(公告)号：US20160111369A1

公开(公告)日：2016-04-21

申请号：US14975830

申请日：2015-12-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L23/528 ,  H01L23/544 ,  H01L23/373 ,  H01L27/06

CPC classification number: H01L23/5286 ,  B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/36 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

Abstract translation: 一种3D IC器件，包括：包括第一单结晶晶体管的第一半导体层，其中所述第一单结晶晶体管通过至少一个包括铝或铜的金属层互连; 第二层，包括第二单结晶晶体管并且覆盖所述至少一个金属层，其中所述至少一个金属层在所述第一半导体层和所述第二层之间; 全球电力网，用于向覆盖第二层的设备分配电力; 以及局部电网以将功率分配给第一单结晶晶体管，其中全局电网通过多个通过第二层通孔连接到本地电网，并且其中通孔具有小于150nm的半径。

公开(公告)号：US20150061036A1

公开(公告)日：2015-03-05

申请号：US14509288

申请日：2014-10-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L27/088 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L23/544

CPC classification number: H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; a second set of external connections overlying the second layer to connect the device to external devices; and an interconnection layer in-between the first layer and the second layer, where the interconnection layer includes copper or aluminum.

Abstract translation: 一种半导体器件，包括：第一层，包括单晶材料和第一晶体管，所述第一晶体管由第一隔离层覆盖; 包括第二晶体管并覆盖第一隔离层的第二层，第二晶体管包括单晶材料; 至少一个接触到所述第二晶体管，其中所述至少一个触点具有小于200nm的直径; 第一层的第一组外部连接，用于将设备连接到外部设备; 第二组外部连接，覆盖第二层以将设备连接到外部设备; 以及位于第一层和第二层之间的互连层，其中互连层包括铜或铝。

公开(公告)号：US12243765B2

公开(公告)日：2025-03-04

申请号：US18829079

申请日：2024-09-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L23/525 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/25 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10D10/01 ,  H10D30/01 ,  H10D30/60 ,  H10D30/68 ,  H10D30/69 ,  H10D64/01 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90 ,  H10D86/00 ,  H10D86/01 ,  H10D88/00 ,  H10D89/10 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10D86/40 ,  H10D86/60

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US12154817B1

公开(公告)日：2024-11-26

申请号：US17942109

申请日：2022-09-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.

公开(公告)号：US20240363385A1

公开(公告)日：2024-10-31

申请号：US18736423

申请日：2024-06-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US12094892B2

公开(公告)日：2024-09-17

申请号：US18110362

申请日：2023-02-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L27/146 ,  H01L25/075 ,  H01L25/16 ,  H01L27/15 ,  H01L33/16 ,  H01L33/62 ,  H10K19/00 ,  H10K39/00 ,  H10K59/00

CPC classification number: H01L27/14603 ,  H01L25/0756 ,  H01L25/167 ,  H01L27/14605 ,  H01L27/156 ,  H01L33/16 ,  H01L33/62 ,  H10K19/201 ,  H10K39/401 ,  H10K59/751

Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), where the second level is disposed on top of the first level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the second level includes a plurality of bond pads, where the bonding structure includes oxide to oxide bonding.