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    METHODS AND APPARATUS TO PARALLELIZE DATA DECOMPRESSION
    185.
    发明申请
    METHODS AND APPARATUS TO PARALLELIZE DATA DECOMPRESSION 有权

    公开(公告)号：US20170141790A1

    公开(公告)日：2017-05-18

    申请号：US15335705

    申请日：2016-10-27

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Sudhir K. Satpathy ,  Sanu K. Mathew

    IPC: H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/4037 ,  H03M7/6005 ,  H03M7/6023

    Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method adjusting a first one of initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; and merging, by executing an instruction with the processor, first decoded data generated by decoding a first segment of the compressed data bitstream starting from the first adjusted starting position with second decoded data generated by decoding a second segment of the compressed data bitstream, the decoding of the second segment starting from a second position in the compressed data bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the compressed data bitstream.

    Techniques to efficiently compute erasure codes having positive and negative coefficient exponents to permit data recovery from more than two failed storage units
    188.
    发明授权
    Techniques to efficiently compute erasure codes having positive and negative coefficient exponents to permit data recovery from more than two failed storage units 有权
    用于有效计算具有正和负系数指数的擦除代码以允许从两个以上故障存储单元进行数据恢复的技术

    公开(公告)号：US09594634B2

    公开(公告)日：2017-03-14

    申请号：US14293791

    申请日：2014-06-02

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Erdinc Ozturk

    IPC: G06F11/10 ,  G06F11/00 ,  H03M13/15 ,  H03M13/00 ,  H03M13/37

    CPC classification number: G06F11/1088 ,  G06F2211/1057 ,  H03M13/1515 ,  H03M13/159 ,  H03M13/373

    Abstract: Erasure code syndrome computation based on Reed Solomon (RS) operations in a Galois field to permit reconstruction of data of more than 2 failed storage units. Syndrome computation may be performed with coefficient exponents that consist of −1, 0, and 1. A product xD of a syndrome is computed as a left-shift of data byte D, and selective compensation based on the most significant bit of D. A product x−1D of a syndrome is computed as a right-shift of data byte D, and selective compensation based on the most significant bit of D. Compensation may include bit-wise XORing shift results with a constant derived from an irreducible polynomial associated with the Galois field. A set of erasure code syndromes may be computed for each of multiple nested arrays of independent storage units. Data reconstruction includes solving coefficients of the syndromes as a Vandermonde matrix.

    Abstract translation: 基于Galois域中的Reed Solomon（RS）操作的擦除码校验子计算，以允许重建超过2个故障存储单元的数据。 综合征计算可以用由-1，0和1组成的系数指数来执行。综合征的乘积xD被计算为数据字节D的左移，并且基于D的最高有效位的选择性补偿。 综合征的乘积x-1D被计算为数据字节D的右移，并且基于D的最高有效位的选择性补偿。补偿可以包括具有从与不相关的多项式相关联的不可约多项式得到的常数的逐位异或移位结果 伽罗瓦领域。 可以为独立存储单元的多个嵌套阵列中的每一个计算一组擦除代码综合征。 数据重建包括求解综合征的系数作为Vandermonde矩阵。

    INSTRUCTION FOR FAST ZUC ALGORITHM PROCESSING
    189.
    发明申请
    INSTRUCTION FOR FAST ZUC ALGORITHM PROCESSING 审中-公开
    用于快速ZUC算法处理的指令

    公开(公告)号：US20170052789A1

    公开(公告)日：2017-02-23

    申请号：US15346410

    申请日：2016-11-08

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F9/38 ,  G06F15/80 ,  G06F9/30

    CPC classification number: G06F9/3867 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3005 ,  G06F9/30098 ,  G06F15/8007 ,  G09C1/00 ,  H04L9/0662 ,  H04L2209/125

    Abstract: Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.

    Abstract translation: 用于执行ZUC流密码操作的矢量指令由处理器的执行电路接收和执行。 执行电路接收第一向量指令以对线性反馈移位寄存器（LFSR）进行更新，并且接收第二向量指令以对有限状态机（FSM）的状态进行更新，其中FSM接收来自 重新排列了LFSR的位。 执行电路在单指令多数据（SIMD）流水线中执行第一向量指令和第二向量指令。

    Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
    190.
    发明授权
    Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction 有权
    处理4操作数SIMD整数乘法累加指令的方法和装置

    公开(公告)号：US09535706B2

    公开(公告)日：2017-01-03

    申请号：US15077093

    申请日：2016-03-22

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC: G06F9/00 ,  G06F9/38 ,  G06F9/30 ,  G06F7/544

    CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/3887

    Abstract: According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.

    Abstract translation: 根据一个实施例，处理器包括指令解码器，用于接收处理多重累加运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。 第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。 所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到 基于第四操作数的累计值。

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