摘要:
An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.
摘要:
Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.
摘要:
Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.
摘要:
Various aspects can be implemented for providing flip-chip interconnect structures for connecting or mounting semiconductor chips to supporting substrates, such as cards, circuit boards, carriers, lead frames, and the like. In general, one aspect can be a method of providing a flip-chip interconnect structure that includes providing a semiconductor work piece that includes one or more bond pads. The method also includes depositing a first non-reflowable layer that has a first melting temperature higher than a predetermined first reflow temperature. The method further includes depositing a reflowable stress relief layer that reflows at the predetermined first reflow temperature. The method additionally includes depositing a second non-reflowable layer that has a second melting temperature higher than the predetermined first reflow temperature such that the deposited reflowable stress relief layer is between the first and the second non-reflowable layers.
摘要:
Structures, methods and materials for making multilayer circuit substrates are disclosed. The structures include bumped structures or microencapsulated conductive particles suitable for use in a lamination process to make a multilayer printed circuit substrate.
摘要:
Bumped semiconductor substrates and methods for forming bumped semiconductor substrates are disclosed. The bumped semiconductor substrates have a polymeric layer, which can serve as a passivation layer for chips derived from the semiconductor substrate.
摘要:
An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.
摘要:
An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.
摘要:
The present technology discloses a multi-die package. The package comprises a lead frame structure and three dies including a first flip chip die, a second flip chip die and a third flip chip die stacked vertically. The first flip chip die is mounted on the bottom surface of the lead frame structure through the flip chip bumps; the second flip chip is mounted on the top surface of the first flip chip die through flip chip bumps; and the third flip chip die is mounted on the top surface of the lead frame structure through flip chip bumps.
摘要:
Improved methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.