公开(公告)号：US08361899B2

公开(公告)日：2013-01-29

申请号：US12970784

申请日：2010-12-16

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L21/44

CPC分类号： H01L23/49575 ,  H01L21/52 ,  H01L21/563 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16258 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/16245 ,  H01L2924/00012 ,  H01L2924/00

摘要： Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

公开(公告)号：US20120153447A1

公开(公告)日：2012-06-21

申请号：US12970784

申请日：2010-12-16

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L21/52 ,  H01L21/563 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16258 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/16245 ,  H01L2924/00012 ,  H01L2924/00

摘要： Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

摘要翻译： 本文描述了组装具有引线框架和/或其它合适衬底的微电子封装的工艺。 在一个实施例中，制造半导体组件的方法包括在引线框架的引线指上形成附接区域和非附着区域。 在回焊期间，附着区域比非附着区域更可润湿焊锡球。 该方法还包括使半导体管芯所携带的焊料球与引线指的附接区域接触，在焊球与引线指的附着区域接触的同时回流焊球，并可控制地使焊球塌陷以建立 半导体管芯和引线框架的引线指之间的电连接。

公开(公告)号：US20120153446A1

公开(公告)日：2012-06-21

申请号：US12970729

申请日：2010-12-16

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L23/36 ,  H01L23/49572 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： Several embodiments of microelectronic packages with enhanced heat dissipation and associated methods of manufacturing are disclosed herein. In one embodiment, a microelectronic package includes a semiconductor die having a first side and a second side opposite the first side and a lead frame proximate the semiconductor die. The lead frame has a lead finger electrically coupled to the first side of the semiconductor die. The microelectronic package also includes an encapsulant at least partially encapsulating the semiconductor die and the lead frame. The encapsulant does not cover at least a portion of the second side of the semiconductor die.

摘要翻译： 本文公开了具有增强的散热和相关制造方法的微电子封装的几个实施例。 在一个实施例中，微电子封装包括具有第一侧和与第一侧相对的第二侧的半导体管芯和靠近半导体管芯的引线框架。 引线框具有电连接到半导体管芯的第一侧的引线指。 微电子封装还包括至少部分地封装半导体管芯和引线框架的密封剂。 密封剂不覆盖半导体管芯的第二侧的至少一部分。

公开(公告)号：US06579474B2

公开(公告)日：2003-06-17

申请号：US09782384

申请日：2001-02-12

申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

IPC分类号： H01B104

CPC分类号： H05K3/363 ,  H01L23/49883 ,  H01L2224/16503 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10666 ,  H05K2203/0425 ,  H05K2203/0455

摘要： A conductive composition, and articles and methods using the conductive composition are disclosed.

摘要翻译： 公开了导电组合物，以及使用导电组合物的制品和方法。

公开(公告)号：US08283758B2

公开(公告)日：2012-10-09

申请号：US12970729

申请日：2010-12-16

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L23/02

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L23/36 ,  H01L23/49572 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： Several embodiments of microelectronic packages with enhanced heat dissipation and associated methods of manufacturing are disclosed herein. In one embodiment, a microelectronic package includes a semiconductor die having a first side and a second side opposite the first side and a lead frame proximate the semiconductor die. The lead frame has a lead finger electrically coupled to the first side of the semiconductor die. The microelectronic package also includes an encapsulant at least partially encapsulating the semiconductor die and the lead frame. The encapsulant does not cover at least a portion of the second side of the semiconductor die.

摘要翻译： 本文公开了具有增强的散热和相关制造方法的微电子封装的几个实施例。 在一个实施例中，微电子封装包括具有第一侧和与第一侧相对的第二侧的半导体管芯和靠近半导体管芯的引线框架。 引线框具有电连接到半导体管芯的第一侧的引线指。 微电子封装还包括至少部分地封装半导体管芯和引线框架的密封剂。 密封剂不覆盖半导体管芯的第二侧的至少一部分。

公开(公告)号：US20120193772A1

公开(公告)日：2012-08-02

申请号：US13016661

申请日：2011-01-28

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L25/07

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49572 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present technology discloses a stacked die package. In one embodiment, a package comprises a first die, a second die, and a leadframe. The first die is electrically coupled to the bottom surface of the leadframe through contact bump/bumps. The second die is electrically coupled to the top surface of the leadframe through wirebond/wires. The second die is mounted on the top surface of the first die.

摘要翻译： 本技术公开了一种堆叠管芯封装。 在一个实施例中，包装包括第一管芯，第二管芯和引线框架。 第一管芯通过接触凸块/凸块电耦合到引线框架的底表面。 第二管芯通过引线/电线电耦合到引线框架的顶表面。 第二模具安装在第一模具的顶表面上。

公开(公告)号：US20120068320A1

公开(公告)日：2012-03-22

申请号：US12886350

申请日：2010-09-20

申请人： Eric YANG ,  Jinghai ZHOU ,  Hunt Hang JIANG

发明人： Eric YANG ,  Jinghai ZHOU ,  Hunt Hang JIANG

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85439 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

摘要翻译： 公开了一种用于实现开关模式功率转换器的集成电路。 所述集成电路至少包括具有电安静表面的第一半导体管芯，用于控制堆叠在具有所述电气安静表面的所述第一半导体管芯上的所述第一半导体管芯的操作的第二半导体管芯和用于支撑所述第一半导体 将所述第一和第二半导体管芯电连接并电耦合到外部电路。

公开(公告)号：US07513037B2

公开(公告)日：2009-04-07

申请号：US11060002

申请日：2005-02-17

申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Michael G. Peters ,  Yasuhito Takahashi

发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Michael G. Peters ,  Yasuhito Takahashi

IPC分类号： H01K3/10

CPC分类号： H01L24/82 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/4602 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for producing a circuit board having an integrated electronic component comprising providing a circuit board substrate having a first substrate surface and a second substrate surface, securing an integrated electronic component to the first substrate surface, and disposing a first dielectric layer on the first substrate surface and over the first integrated electronic component. The method additionally includes disposing a metallic layer on the first dielectric layer to produce an integrated electronic component assembly, producing in the integrated electronic component assembly at least one via having a metal lining in contact with the metallic layer, and disposing a second dielectric layer over the via and over the metallic layer. At least one metal-lined opening is formed in the second dielectric layer and in the first dielectric layer to expose at least part of the integrated electronic component, and to couple the metal lining of the opening to the first integrated electronic component to produce a circuit board having at least one integrated electronic component. A multi-layer printed circuit board having at least one prefabricated, integrated electronic component.

摘要翻译： 一种具有集成电子部件的电路板的制造方法，其特征在于，具备：提供具有第一基板表面和第二基板表面的电路板基板，将集成电子部件固定到所述第一基板表面，以及将第一电介质层设置在所述第一基板 表面和第一个集成电子部件。 该方法还包括在第一电介质层上设置金属层以产生集成的电子部件组件，在集成电子部件组件中产生具有与金属层接触的金属衬里的至少一个通孔，并且将第二电介质层设置在 通孔和金属层上。 在第二电介质层和第一电介质层中形成至少一个金属衬里的开口以暴露集成电子元件的至少一部分，并将开口的金属衬里连接到第一集成电子元件以产生电路 具有至少一个集成电子部件的板。 具有至少一个预制的集成电子部件的多层印刷电路板。

公开(公告)号：US6163957A

公开(公告)日：2000-12-26

申请号：US192003

申请日：1998-11-13

申请人： Hunt Hang Jiang ,  Thomas Massingill ,  Mark Thomas McCormack ,  Michael Guang-Tzong Lee

发明人： Hunt Hang Jiang ,  Thomas Massingill ,  Mark Thomas McCormack ,  Michael Guang-Tzong Lee

IPC分类号： H01R12/04 ,  H01L21/48 ,  H01L23/538 ,  H05K1/14 ,  H05K3/00 ,  H05K3/12 ,  H05K3/28 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC分类号： H05K3/4617 ,  H01L21/4857 ,  H01L23/5385 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/1216 ,  H05K3/28 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0394 ,  H05K2203/0191 ,  H05K2203/1453 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T428/31678 ,  Y10T428/31681 ,  H01L2924/00

摘要： Multilayer circuit lamination methods and circuit layer structures are disclosed which enable one to manufacture high-density multichip module boards and the like at lower cost, with higher yield, with higher signal densities, and with fewer processing steps.

摘要翻译： 公开了多层电路层叠方法和电路层结构，其能够以更低的成本，更高的产量，更高的信号密度和更少的处理步骤来制造高密度多芯片模块板等。

公开(公告)号：US08604597B2

公开(公告)日：2013-12-10

申请号：US13096634

申请日：2011-04-28

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/17165 ,  H01L2224/48227 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： The present technology discloses a multi-die package. The package comprises a lead frame structure and three dies including a first flip chip die, a second flip chip die and a third flip chip die stacked vertically. The first flip chip die is mounted on the bottom surface of the lead frame structure through the flip chip bumps; the second flip chip is mounted on the top surface of the first flip chip die through flip chip bumps; and the third flip chip die is mounted on the top surface of the lead frame structure through flip chip bumps.

摘要翻译： 本技术公开了一种多管芯封装。 封装包括引线框架结构和三个管芯，其包括垂直堆叠的第一倒装芯片管芯，第二倒装芯片管芯和第三倒装芯片管芯。 第一倒装芯片通过倒装芯片凸块安装在引线框架结构的底表面上; 第二倒装芯片通过倒装芯片凸块安装在第一倒装芯片的顶表面上; 并且第三倒装芯片裸片通过倒装芯片凸块安装在引线框架结构的顶表面上。