公开(公告)号：US06326555B1

公开(公告)日：2001-12-04

申请号：US09259126

申请日：1999-02-26

申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Thomas J. Massingill ,  Solomon I. Beilin

发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Thomas J. Massingill ,  Solomon I. Beilin

IPC分类号： H05K103

CPC分类号： H05K3/462 ,  H05K3/3484 ,  H05K2201/09536 ,  H05K2203/0191 ,  H05K2203/043 ,  H05K2203/0568 ,  Y10T29/49128

摘要： Structures, methods and materials for making multilayer circuit substrates are disclosed. The structures include bumped structures or microencapsulated conductive particles suitable for use in a lamination process to make a multilayer printed circuit substrate.

摘要翻译： 公开了用于制造多层电路基板的结构，方法和材料。 这些结构包括适于用于层压工艺以制造多层印刷电路基板的凸起结构或微胶囊化导电颗粒。

公开(公告)号：US06281040B1

公开(公告)日：2001-08-28

申请号：US09397614

申请日：1999-09-16

申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

IPC分类号： H01L2144

CPC分类号： H05K3/363 ,  H01L23/49883 ,  H01L2224/16503 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10666 ,  H05K2203/0425 ,  H05K2203/0455

摘要： Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.

摘要翻译： 公开了制造电路基板和电气组件的方法。 导电组合物设置在相对的导电区域之间，并且可以被固化以形成通孔结构。 导电组合物包括导电颗粒和载体。 载体可以包括助熔剂和在25℃下粘度小于约1000厘泊的环氧官能树脂。

公开(公告)号：US06579474B2

公开(公告)日：2003-06-17

申请号：US09782384

申请日：2001-02-12

申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

IPC分类号： H01B104

CPC分类号： H05K3/363 ,  H01L23/49883 ,  H01L2224/16503 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10666 ,  H05K2203/0425 ,  H05K2203/0455

摘要： A conductive composition, and articles and methods using the conductive composition are disclosed.

摘要翻译： 公开了导电组合物，以及使用导电组合物的制品和方法。

公开(公告)号：US6054761A

公开(公告)日：2000-04-25

申请号：US203126

申请日：1998-12-01

申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

IPC分类号： C08K3/00 ,  C08L63/00 ,  H01L23/498 ,  H05K3/40 ,  H05K3/46 ,  H01L23/04

CPC分类号： H05K3/363 ,  H01L23/49883 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H01L2224/16503 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10666 ,  H05K2203/0425 ,  H05K2203/0455 ,  H05K3/321 ,  H05K3/4623

摘要： Printed circuit substrates and electrical assemblies including a conductive composition are disclosed. The printed circuit substrate and the electrical assembly embodiments comprise a first conducting region and a second conducting region. A dielectric layer is disposed between the first and second conducting regions. An aperture is disposed in the dielectric layer and a via structure including the conductive composition is disposed in the aperture. The conductive composition is preferably in a cured state and electrically communicates with the first and second conducting regions. In preferred embodiments, the conductive composition comprises conductive particles in an amount of at least about 75 wt. % based on the weight of the composition. At least 50% by weight of the conductive particles have melting points of less than about 400.degree. C. The composition further includes a carrier including an epoxy-functional resin in an amount of at least about 50 wt. % based on the weight of the carrier, and a fluxing agent in an amount of at least about 0.1 wt % based on the weight of the carrier. The epoxy functional resin can have a viscosity of less than about 1000 centipoise at 25.degree. C.

摘要翻译： 公开了印刷电路基板和包括导电组合物的电气组件。 印刷电路基板和电组件实施例包括第一导电区域和第二导电区域。 电介质层设置在第一和第二导电区域之间。 在电介质层中设置孔，并且包括导电组合物的通孔结构设置在孔中。 导电组合物优选处于固化状态并与第一和第二导电区域电连通。 在优选的实施方案中，导电组合物包含至少约75wt。 基于组合物的重量％。 至少50重量％的导电颗粒具有小于约400℃的熔点。该组合物还包括载体，其包含至少约50重量％的量的环氧官能树脂。 基于载体的重量，以及基于载体重量的至少约0.1重量％的助熔剂。 环氧官能树脂在25℃下的粘度可以小于约1000厘泊

公开(公告)号：US06271107B1

公开(公告)日：2001-08-07

申请号：US09282788

申请日：1999-03-31

申请人： Thomas Massingill ,  Mark Thomas McCormack ,  Hunt Hang Jiang

发明人： Thomas Massingill ,  Mark Thomas McCormack ,  Hunt Hang Jiang

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2224/73203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/0032 ,  H05K3/3484 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2924/00014

摘要： Bumped semiconductor substrates and methods for forming bumped semiconductor substrates are disclosed. The bumped semiconductor substrates have a polymeric layer, which can serve as a passivation layer for chips derived from the semiconductor substrate.

摘要翻译： 公开了凸起的半导体衬底和用于形成凸起的半导体衬底的方法。 凸起的半导体衬底具有聚合物层，其可以用作来自半导体衬底的芯片的钝化层。

公开(公告)号：US07513037B2

公开(公告)日：2009-04-07

申请号：US11060002

申请日：2005-02-17

申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Michael G. Peters ,  Yasuhito Takahashi

发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Michael G. Peters ,  Yasuhito Takahashi

IPC分类号： H01K3/10

CPC分类号： H01L24/82 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/4602 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for producing a circuit board having an integrated electronic component comprising providing a circuit board substrate having a first substrate surface and a second substrate surface, securing an integrated electronic component to the first substrate surface, and disposing a first dielectric layer on the first substrate surface and over the first integrated electronic component. The method additionally includes disposing a metallic layer on the first dielectric layer to produce an integrated electronic component assembly, producing in the integrated electronic component assembly at least one via having a metal lining in contact with the metallic layer, and disposing a second dielectric layer over the via and over the metallic layer. At least one metal-lined opening is formed in the second dielectric layer and in the first dielectric layer to expose at least part of the integrated electronic component, and to couple the metal lining of the opening to the first integrated electronic component to produce a circuit board having at least one integrated electronic component. A multi-layer printed circuit board having at least one prefabricated, integrated electronic component.

摘要翻译： 一种具有集成电子部件的电路板的制造方法，其特征在于，具备：提供具有第一基板表面和第二基板表面的电路板基板，将集成电子部件固定到所述第一基板表面，以及将第一电介质层设置在所述第一基板 表面和第一个集成电子部件。 该方法还包括在第一电介质层上设置金属层以产生集成的电子部件组件，在集成电子部件组件中产生具有与金属层接触的金属衬里的至少一个通孔，并且将第二电介质层设置在 通孔和金属层上。 在第二电介质层和第一电介质层中形成至少一个金属衬里的开口以暴露集成电子元件的至少一部分，并将开口的金属衬里连接到第一集成电子元件以产生电路 具有至少一个集成电子部件的板。 具有至少一个预制的集成电子部件的多层印刷电路板。

公开(公告)号：US6163957A

公开(公告)日：2000-12-26

申请号：US192003

申请日：1998-11-13

申请人： Hunt Hang Jiang ,  Thomas Massingill ,  Mark Thomas McCormack ,  Michael Guang-Tzong Lee

发明人： Hunt Hang Jiang ,  Thomas Massingill ,  Mark Thomas McCormack ,  Michael Guang-Tzong Lee

IPC分类号： H01R12/04 ,  H01L21/48 ,  H01L23/538 ,  H05K1/14 ,  H05K3/00 ,  H05K3/12 ,  H05K3/28 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC分类号： H05K3/4617 ,  H01L21/4857 ,  H01L23/5385 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/1216 ,  H05K3/28 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0394 ,  H05K2203/0191 ,  H05K2203/1453 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T428/31678 ,  Y10T428/31681 ,  H01L2924/00

摘要： Multilayer circuit lamination methods and circuit layer structures are disclosed which enable one to manufacture high-density multichip module boards and the like at lower cost, with higher yield, with higher signal densities, and with fewer processing steps.

摘要翻译： 公开了多层电路层叠方法和电路层结构，其能够以更低的成本，更高的产量，更高的信号密度和更少的处理步骤来制造高密度多芯片模块板等。

公开(公告)号：US20090108443A1

公开(公告)日：2009-04-30

申请号：US11928218

申请日：2007-10-30

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2924/00

摘要： Various aspects can be implemented for providing flip-chip interconnect structures for connecting or mounting semiconductor chips to supporting substrates, such as cards, circuit boards, carriers, lead frames, and the like. In general, one aspect can be a method of providing a flip-chip interconnect structure that includes providing a semiconductor work piece that includes one or more bond pads. The method also includes depositing a first non-reflowable layer that has a first melting temperature higher than a predetermined first reflow temperature. The method further includes depositing a reflowable stress relief layer that reflows at the predetermined first reflow temperature. The method additionally includes depositing a second non-reflowable layer that has a second melting temperature higher than the predetermined first reflow temperature such that the deposited reflowable stress relief layer is between the first and the second non-reflowable layers.

摘要翻译： 可以实现各种方面来提供用于将半导体芯片连接或安装到诸如卡，电路板，载体，引线框架等的支撑基板的倒装芯片互连结构。 通常，一个方面可以是提供倒装芯片互连结构的方法，其包括提供包括一个或多个接合焊盘的半导体工件。 该方法还包括沉积具有高于预定的第一回流温度的第一熔化温度的第一不可回流层。 该方法还包括沉积在预定的第一回流温度下回流的可回流应力消除层。 该方法另外包括沉积具有高于预定的第一回流温度的第二熔解温度的第二不可回流层，使得沉积的可回流应力消除层位于第一和第二不可回流层之间。

公开(公告)号：US08361899B2

公开(公告)日：2013-01-29

申请号：US12970784

申请日：2010-12-16

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L21/44

CPC分类号： H01L23/49575 ,  H01L21/52 ,  H01L21/563 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16258 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/16245 ,  H01L2924/00012 ,  H01L2924/00

摘要： Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

公开(公告)号：US20120153447A1

公开(公告)日：2012-06-21

申请号：US12970784

申请日：2010-12-16

申请人： Hunt Hang Jiang

发明人： Hunt Hang Jiang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L21/52 ,  H01L21/563 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16258 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/16245 ,  H01L2924/00012 ,  H01L2924/00

摘要： Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

摘要翻译： 本文描述了组装具有引线框架和/或其它合适衬底的微电子封装的工艺。 在一个实施例中，制造半导体组件的方法包括在引线框架的引线指上形成附接区域和非附着区域。 在回焊期间，附着区域比非附着区域更可润湿焊锡球。 该方法还包括使半导体管芯所携带的焊料球与引线指的附接区域接触，在焊球与引线指的附着区域接触的同时回流焊球，并可控制地使焊球塌陷以建立 半导体管芯和引线框架的引线指之间的电连接。