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公开(公告)号：US08670637B2
公开(公告)日：2014-03-11
申请号：US13209228
申请日：2011-08-12
申请人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
发明人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
IPC分类号： G02B6/12
摘要： An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.
摘要翻译： 集成电路结构包括：包括前表面和后表面的半导体芯片; 从半导体芯片的背面延伸到半导体芯片的通孔，其中所述通孔是透光的; 和半导体芯片中的光子检测器，并暴露于通孔。
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公开(公告)号：US20140021594A1
公开(公告)日：2014-01-23
申请号：US13554839
申请日：2012-07-20
申请人： Ming-Chih Yew , Wen-Yi Lin , Jiun Yi Wu , Po-Yao Lin
发明人： Ming-Chih Yew , Wen-Yi Lin , Jiun Yi Wu , Po-Yao Lin
IPC分类号： H01L23/495 , H05K3/10 , H05K1/11
CPC分类号： H01L23/49811 , H01L21/563 , H01L23/147 , H01L23/3128 , H01L23/3142 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/562 , H01L24/16 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/10152 , H01L2224/13099 , H01L2224/13147 , H01L2224/16227 , H01L2224/16237 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/81193 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H05K1/0271 , H05K2201/0989 , Y10T29/49155 , H01L2924/00014 , H01L2924/00012 , H01L2224/16225 , H01L2924/00 , H01L2224/81805
摘要： Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.
摘要翻译： 公开了用于半导体器件的封装结构和方法。 在一个实施例中，用于封装半导体器件的衬底包括芯衬底，设置在芯衬底上的绝缘材料以及设置在绝缘材料中的导线。 接触垫设置在绝缘材料和导电线之上。 接触垫设置在芯基板的集成电路安装区域中。 在绝缘材料上设置焊接掩模限定（SMD）材料。 接触垫的一部分通过SMD材料的开口露出。 应力消除结构（SRS）被布置在靠近接触垫的SMD材料中。 SRS完全设置在芯基板的集成电路安装区域中。
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公开(公告)号：US20130082372A1
公开(公告)日：2013-04-04
申请号：US13250606
申请日：2011-09-30
申请人： Wen-Yi Lin , Ming-Chih Yew , Po-Yao Lin , Jing Ruei Lu , Jiun Yi Wu
发明人： Wen-Yi Lin , Ming-Chih Yew , Po-Yao Lin , Jing Ruei Lu , Jiun Yi Wu
CPC分类号： H01L25/50 , H01L23/36 , H01L23/3675 , H01L23/3677 , H01L23/42 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/105 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17519 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/48465 , H01L2224/73253 , H01L2224/73265 , H01L2224/81801 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.
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公开(公告)号：US20120217632A1
公开(公告)日：2012-08-30
申请号：US13035586
申请日：2011-02-25
申请人： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
发明人： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
IPC分类号： H01L23/498
CPC分类号： H01L24/16 , H01L23/49816 , H01L23/49838 , H01L24/13 , H01L24/17 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16013 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.
摘要翻译： 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。
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公开(公告)号：US08005326B2
公开(公告)日：2011-08-23
申请号：US12170570
申请日：2008-07-10
申请人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
发明人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
IPC分类号： G02B6/12
摘要： An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.
摘要翻译： 集成电路结构包括：包括前表面和后表面的半导体芯片; 从半导体芯片的背面延伸到半导体芯片的通孔，其中所述通孔是透光的; 和半导体芯片中的光子检测器，并暴露于通孔。
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公开(公告)号：US09691636B2
公开(公告)日：2017-06-27
申请号：US13433210
申请日：2012-03-28
申请人： Jiun Yi Wu
发明人： Jiun Yi Wu
IPC分类号： H01L21/48 , H01L21/56 , H01L23/14 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/00 , H01L25/10
CPC分类号： H01L25/105 , H01L21/4803 , H01L21/4846 , H01L21/563 , H01L23/14 , H01L23/145 , H01L23/147 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49866 , H01L23/5384 , H01L23/5385 , H01L25/50 , H01L2224/16225 , H01L2224/32225 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1305 , H01L2924/13091 , H01L2924/15321 , H01L2924/00
摘要： The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improve mechanical strength of the package.
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公开(公告)号：US09607936B2
公开(公告)日：2017-03-28
申请号：US12619468
申请日：2009-11-16
申请人： Ching-Wen Hsiao , Jiun Yi Wu , Ru-Ying Huang , Chen-Shien Chen
发明人： Ching-Wen Hsiao , Jiun Yi Wu , Ru-Ying Huang , Chen-Shien Chen
IPC分类号： H01L23/488 , H01L23/498 , H01L23/00 , H05K3/34
CPC分类号： H01L23/49816 , H01L23/49827 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/1146 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K3/3463 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.
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公开(公告)号：US08847369B2
公开(公告)日：2014-09-30
申请号：US13554839
申请日：2012-07-20
申请人： Ming-Chih Yew , Wen-Yi Lin , Jiun Yi Wu , Po-Yao Lin
发明人： Ming-Chih Yew , Wen-Yi Lin , Jiun Yi Wu , Po-Yao Lin
CPC分类号： H01L23/49811 , H01L21/563 , H01L23/147 , H01L23/3128 , H01L23/3142 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/562 , H01L24/16 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/10152 , H01L2224/13099 , H01L2224/13147 , H01L2224/16227 , H01L2224/16237 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/81193 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H05K1/0271 , H05K2201/0989 , Y10T29/49155 , H01L2924/00014 , H01L2924/00012 , H01L2224/16225 , H01L2924/00 , H01L2224/81805
摘要： Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.
摘要翻译： 公开了用于半导体器件的封装结构和方法。 在一个实施例中，用于封装半导体器件的衬底包括芯衬底，设置在芯衬底上的绝缘材料以及设置在绝缘材料中的导线。 接触垫设置在绝缘材料和导电线之上。 接触垫设置在芯基板的集成电路安装区域中。 在绝缘材料上设置焊接掩模限定（SMD）材料。 接触垫的一部分通过SMD材料的开口露出。 应力消除结构（SRS）被布置在靠近接触垫的SMD材料中。 SRS完全设置在芯基板的集成电路安装区域中。
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19.发明申请公开(公告)号：US20140021605A1
公开(公告)日：2014-01-23
申请号：US13552375
申请日：2012-07-18
申请人： Chen-Hua Yu , Yung Ching Chen , Chien-Hsun Lee , Jiun Yi Wu , Mirng-Ji Lii , Ming-Da Cheng
发明人： Chen-Hua Yu , Yung Ching Chen , Chien-Hsun Lee , Jiun Yi Wu , Mirng-Ji Lii , Ming-Da Cheng
CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/68778 , H01L23/3142 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13164 , H01L2224/13169 , H01L2224/16058 , H01L2224/16148 , H01L2224/16238 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/92125 , H01L2225/0651 , H01L2225/06513 , H01L2225/0652 , H01L2225/06548 , H01L2225/06565 , H01L2225/06572 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19107 , H01L2924/2064 , H01L2924/20641 , H01L2924/20642 , H01L2924/20643 , H01L2924/20644 , H01L2924/20645 , H01L2224/16225 , H01L2924/00012 , H01L2924/014
摘要： Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint.
摘要翻译： 封装封装（PoP）器件和封装半导体管芯的方法被公开。 PoP器件包括第一封装管芯和耦合到第一封装管芯的第二封装管芯。 在第一封装模具和第二封装模具之间设置金属凸块凸块。 金属柱凸块包括一个棒状区域，一个耦合到该棒状区域的第一端的第一球形区域和一个耦合到该棒状区域的第二端的第二球形区域。 金属柱凸块包括部分嵌入焊点中的部分。
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公开(公告)号：US20130200517A1
公开(公告)日：2013-08-08
申请号：US13433210
申请日：2012-03-28
申请人： Jiun Yi WU
发明人： Jiun Yi WU
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/105 , H01L21/4803 , H01L21/4846 , H01L21/563 , H01L23/14 , H01L23/145 , H01L23/147 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49866 , H01L23/5384 , H01L23/5385 , H01L25/50 , H01L2224/16225 , H01L2224/32225 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1305 , H01L2924/13091 , H01L2924/15321 , H01L2924/00
摘要： The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improve mechanical strength of the package.
摘要翻译： 在本公开中提供了使用插入器框架形成PoP封装的机构。 通过使用具有一种或多种添加剂的基底来调节基材的性质来形成中介层框架。 插入器框架具有衬有导电层的开口，以在相邻封装上的焊球形成通过衬底通孔（TSV）。 内插器框架能够减少TSV的间距，热膨胀系数（CTE）的失配，焊接接头的短路和分层，并提高封装的机械强度。
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