公开(公告)号：US20130087914A1

公开(公告)日：2013-04-11

申请号：US13253845

申请日：2011-10-05

申请人： Chung-Ying YANG ,  Hsien-Wei CHEN ,  Tsung-Yuan YU ,  Shih-Wei LIANG

发明人： Chung-Ying YANG ,  Hsien-Wei CHEN ,  Tsung-Yuan YU ,  Shih-Wei LIANG

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/3142 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76895 ,  H01L23/3114 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2224/05552

摘要： A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.

摘要翻译： 晶片级芯片级封装（WLCSP）包括具有接触焊盘的有源表面和侧表面的半导体器件。 模具覆盖半导体器件的侧表面。 RDL结构包括电连接到接触焊盘并在半导体器件的有源表面上延伸的第一PPI线。 UBM层形成在第一PPI线之上并电连接到第一PPI线。 密封环结构围绕模具上的半导体器件的上周围延伸。 密封环结构包括在与第一PPI线和UBM层中的至少一个相同的高度上延伸的密封层。 制造WLCSP的方法包括通过在模制的半导体器件上同时形成互连线和密封层来形成再布线层压结构。

公开(公告)号：US20120261662A1

公开(公告)日：2012-10-18

申请号：US13085745

申请日：2011-04-13

申请人： Shih-Wei LIANG ,  Yu-Wen LIU ,  Hsien-Wei CHEN

发明人： Shih-Wei LIANG ,  Yu-Wen LIU ,  Hsien-Wei CHEN

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L22/34 ,  H01L23/522 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05572 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2224/05552

摘要： An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer orprinted circuit board forming a portion of the test circuit.

摘要翻译： 一种集成电路系统，包括第一集成电路和第二集成电路，插入器或印刷电路板中的至少一个。 第一集成电路还包括布线堆叠，电连接到布线堆叠的接合焊盘以及形成在接合焊盘上的凸块球。 布线堆叠和接合焊盘的第一部分形成功能电路，并且布线堆叠和接合焊盘的第二部分形成测试电路。 凸块球的一部分包括虚拟凸块球。 虚拟凸块球电连接到布线堆叠的第二部分和接合垫。 形成测试电路的一部分的第二集成电路，插入器或印刷电路板中的至少一个。

公开(公告)号：US08237160B2

公开(公告)日：2012-08-07

申请号：US13198408

申请日：2011-08-04

申请人： Hsien-Wei Chen ,  Chung-Ying Yang ,  Ying-Ju Chen ,  Shih-Wei Liang ,  Ching-Jung Yang

发明人： Hsien-Wei Chen ,  Chung-Ying Yang ,  Ying-Ju Chen ,  Shih-Wei Liang ,  Ching-Jung Yang

IPC分类号： H01L23/58

CPC分类号： H01L27/0203 ,  H01L22/34 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.

摘要翻译： 半导体芯片包括角部应力消除（CSR）区域。 增强的结构将密封环结构的侧面连接到包围CSR区域。 被测设备（DUT）结构设置在CSR区域上。 一组探针垫结构设置在CSR区域上。 探针焊盘结构中的两个电连接到DUT结构。

公开(公告)号：US20120092033A1

公开(公告)日：2012-04-19

申请号：US12903984

申请日：2010-10-13

申请人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： G01R31/00 ,  G01R27/00 ,  G01R29/26

CPC分类号： G01R31/2648 ,  G01R31/002 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2224/13

摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

摘要翻译： 提供了一种用于测试未封装的半导体晶片的测试结构。 测试结构包括耦合到半导体晶片的互连结构的施力部件。 力施加部件可操作以向半导体晶片施加力。 测试结构还包括耦合到互连结构的第一和第二测试部分。 第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。 第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

公开(公告)号：US20130292831A1

公开(公告)日：2013-11-07

申请号：US13463667

申请日：2012-05-03

申请人： Ming-Kai Liu ,  Shih-Wei Liang ,  Hsien-Wei Chen ,  Kai-Chiang Wu

发明人： Ming-Kai Liu ,  Shih-Wei Liang ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC分类号： H01L23/52 ,  H01L23/488 ,  H01L21/50

CPC分类号： H01L24/17 ,  H01L21/50 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/52 ,  H01L24/13 ,  H01L24/15 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81986 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805

摘要： Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.

公开(公告)号：US20130228897A1

公开(公告)日：2013-09-05

申请号：US13410195

申请日：2012-03-01

申请人： Hsien-Wei Chen ,  Shih-Wei Liang

发明人： Hsien-Wei Chen ,  Shih-Wei Liang

IPC分类号： H01L23/58

CPC分类号： H01L23/528 ,  H01L21/311 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/0502 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06131 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/05947

摘要： Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.

公开(公告)号：US20110284843A1

公开(公告)日：2011-11-24

申请号：US13198408

申请日：2011-08-04

申请人： Hsien-Wei Chen ,  Chung-Ying Yang ,  Ying-Ju Chen ,  Shih-Wei Liang ,  Ching-Jung Yang

发明人： Hsien-Wei Chen ,  Chung-Ying Yang ,  Ying-Ju Chen ,  Shih-Wei Liang ,  Ching-Jung Yang

IPC分类号： H01L23/528

CPC分类号： H01L27/0203 ,  H01L22/34 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.

摘要翻译： 半导体芯片包括角部应力消除（CSR）区域。 增强的结构将密封环结构的侧面连接到包围CSR区域。 被测设备（DUT）结构设置在CSR区域上。 一组探针垫结构设置在CSR区域上。 探针焊盘结构中的两个电连接到DUT结构。

公开(公告)号：US08581400B2

公开(公告)日：2013-11-12

申请号：US13272540

申请日：2011-10-13

申请人： Shih-Wei Liang ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu ,  Mirng-Ji Lii

发明人： Shih-Wei Liang ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu ,  Mirng-Ji Lii

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L21/76841 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.

摘要翻译： 半导体器件包括依次形成在半导体衬底上的钝化层，第一保护层，互连层和第二保护层。 互连层具有暴露部分，其上形成有阻挡层和焊料凸块。 钝化层，第一保护层，互连层和第二保护层中的至少一个包括形成在导电焊盘区域外的区域中的至少一个槽。

公开(公告)号：US20130043598A1

公开(公告)日：2013-02-21

申请号：US13212536

申请日：2011-08-18

申请人： Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Tsung-Yuan YU ,  Shih-Wei LIANG

发明人： Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Tsung-Yuan YU ,  Shih-Wei LIANG

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/291 ,  H01L23/3192 ,  H01L23/5226 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48666 ,  H01L2224/48681 ,  H01L2224/48684 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.

摘要翻译： 提供了形成接合焊盘结构的机理。 接合焊盘具有凹陷区域，该凹陷区域由接合焊盘下方的钝化层中的开口形成。 上钝化层至少覆盖接合焊盘的凹陷区域，以减少凹陷区域中图案化和/或蚀刻残留物的捕获。 结果，焊盘腐蚀的可能性降低。

公开(公告)号：US08912668B2

公开(公告)日：2014-12-16

申请号：US13410195

申请日：2012-03-01

申请人： Hsien-Wei Chen ,  Shih-Wei Liang

发明人： Hsien-Wei Chen ,  Shih-Wei Liang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/528 ,  H01L21/311 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/0502 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06131 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/05947

摘要： Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.

摘要翻译： 公开了用于芯片级封装的电连接。 在一个实施例中，半导体器件包括设置在衬底上的后钝化层，该衬底具有第一热方向的热膨胀失配系数。 半导体器件包括穿过后钝化层的第一开口，第一开口包括多个细长孔。 多个细长孔中最长的一个包括第一尺寸，其中第一尺寸基本垂直于热膨胀失配系数的第一方向排列。