公开(公告)号：US08999821B2

公开(公告)日：2015-04-07

申请号：US14269417

申请日：2014-05-05

Applicant: Applied Materials, Inc.

Inventor： Adam Brand ,  Bingxi Wood ,  Errol Sanchez ,  Yihwan Kim ,  Yi-Chiau Huang ,  John Boland

IPC: H01L21/20 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/0262 ,  H01L29/66795

Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.

Abstract translation: 描述形成场效应晶体管的鳍结构的方法。 所述方法可以包括将芯棒图案化在衬底的表面上，以及在图案化心轴的暴露表面上沉积高迁移率沟道材料外延层的操作。 外延层在图案化心轴的相邻列之间留下间隙，并且介电材料可以沉积在图案化心轴的相邻列之间的间隙中。 所述方法还可以包括平坦化外延层以形成平坦化的外延层并暴露图案化心轴的列，以及蚀刻图案化心轴和电介质材料的暴露的柱的至少一部分，以暴露出至少一部分 形成翅片结构的平坦化外延层。

公开(公告)号：US12068155B2

公开(公告)日：2024-08-20

申请号：US17396371

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying Wu ,  Zhiyuan Ye ,  Xuebin Li ,  Sathya Chary ,  Yi-Chiau Huang ,  Saurabh Chopra

IPC: H01L21/02 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L21/02211 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/04

Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly surfaces with reduced or negligible growth on surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

公开(公告)号：US11948796B2

公开(公告)日：2024-04-02

申请号：US17616131

申请日：2020-06-10

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Chen-Ying Wu ,  Abhishek Dube ,  Chia Cheng Chin ,  Saurabh Chopra

IPC: C30B25/10 ,  C23C16/06 ,  C30B25/18 ,  C30B29/52 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/02636 ,  C23C16/06 ,  C30B25/18 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823418 ,  H01L29/0847 ,  H01L21/02381 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/823431 ,  H01L29/785

Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

公开(公告)号：US11848226B2

公开(公告)日：2023-12-19

申请号：US17183146

申请日：2021-02-23

Applicant: Applied Materials, Inc.

Inventor： Anhthu Ngo ,  Zuoming Zhu ,  Balasubramanian Ramachandran ,  Paul Brillhart ,  Edric Tong ,  Anzhong Chang ,  Kin Pong Lo ,  Kartik Shah ,  Schubert S. Chu ,  Zhepeng Cong ,  James Francis Mack ,  Nyi O. Myo ,  Kevin Joseph Bautista ,  Xuebin Li ,  Yi-Chiau Huang ,  Zhiyuan Ye

IPC: H01L21/687 ,  C30B25/12 ,  B05C13/02 ,  B05C13/00 ,  H01L21/673 ,  C23C16/458

CPC classification number: H01L21/68735 ,  B05C13/00 ,  B05C13/02 ,  C30B25/12 ,  H01L21/67326 ,  H01L21/6875 ,  H01L21/68785 ,  C23C16/4585

Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.

公开(公告)号：US11152479B2

公开(公告)日：2021-10-19

申请号：US16773848

申请日：2020-01-27

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Xuebin Li ,  Abhishek Dube ,  Yi-Chiau Huang ,  Andy Lo ,  Patricia M. Liu ,  Sanjay Natarajan ,  Saurabh Chopra

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78 ,  H01L29/417

Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

公开(公告)号：US10128110B2

公开(公告)日：2018-11-13

申请号：US15882939

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Yi-Chiau Huang ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

公开(公告)号：US09966438B2

公开(公告)日：2018-05-08

申请号：US15418286

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Hua Chung ,  Sheng-Chin Kung ,  Xuebin Li

IPC: H01L21/02 ,  H01L29/167 ,  H01L29/161 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205

CPC classification number: H01L29/167 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02656 ,  H01L21/02661 ,  H01L21/02667 ,  H01L21/2018 ,  H01L21/2033 ,  H01L21/2053 ,  H01L21/2252 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67184 ,  H01L21/67207 ,  H01L29/161 ,  H01L29/785

Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

公开(公告)号：US09929055B2

公开(公告)日：2018-03-27

申请号：US15391623

申请日：2016-12-27

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Hua Chung ,  Jenn-Yue Wang ,  Xuebin Li ,  Yi-Chiau Huang ,  Schubert S. Chu

IPC: H01L21/20 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

公开(公告)号：US09721792B2

公开(公告)日：2017-08-01

申请号：US14465330

申请日：2014-08-21

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Yihwan Kim

IPC: H01L21/02 ,  H01L21/67

CPC classification number: H01L21/02587 ,  H01L21/0237 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02524 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/67115

Abstract: Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.

公开(公告)号：US09029264B2

公开(公告)日：2015-05-12

申请号：US13779713

申请日：2013-02-27

Applicant: Applied Materials, Inc.

Inventor： Errol Antonio C. Sanchez ,  Yi-Chiau Huang

IPC: H01L21/311 ,  C23C16/513 ,  C23C16/30 ,  C23C16/06 ,  C23C16/44

CPC classification number: C23C16/513 ,  C23C16/06 ,  C23C16/30 ,  C23C16/4412

Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.

Abstract translation: 本文公开了在基底上沉积含锡层的方法。 在一些实施例中，在基底上沉积含锡层的方法可以包括使包含锡卤化物的锡源流入反应体积; 使氢等离子体流入反应体积; 在锡源和氢等离子体的反应体积内形成一种或多种锡氢化物; 以及使用所述一种或多种锡氢化物将所述含锡层沉积在所述衬底的第一表面上。