公开(公告)号：US09577100B2

公开(公告)日：2017-02-21

申请号：US14305543

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Kern Rim ,  Henry K. Utomo

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract translation: 一种半导体器件，包括至少一个包含硅的悬浮沟道结构，以及存在于悬挂沟道结构上的栅极结构。 至少一个栅极电介质层存在于悬置沟道结构周围，并且至少一个栅极导体存在于至少一个栅极电介质层上。 源极和漏极结构可以由包括硅和锗的材料组成。 源极和漏极结构通过硅包覆层与悬浮沟道结构的源极和漏极端部接触。

公开(公告)号：US09524986B2

公开(公告)日：2016-12-20

申请号：US14315362

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Ramachandra Divakaruni ,  Judson R. Holt ,  Arvind Kumar ,  Unoh Kwon

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L21/306 ,  H01L21/311 ,  H01L29/16 ,  H01L21/3105

CPC classification number: H01L27/1207 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.

Abstract translation: 本发明一般涉及半导体器件，更具体地说，涉及通过捕获外延期间发生的晶格位错而在绝缘体上硅绝缘体（SOI）衬底上形成高迁移率鳍状场效应晶体管（finFET）鳍的结构和方法 在半导体层中形成的凹部中生长。 结晶晶格位错可以保留在薄的隔离层下方，从而减少器件厚度以及高纵横比蚀刻和鳍形成的需要。

公开(公告)号：US09373690B2

公开(公告)日：2016-06-21

申请号：US14826466

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

公开(公告)号：US09293461B2

公开(公告)日：2016-03-22

申请号：US13780003

申请日：2013-02-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Unoh Kwon ,  Michael P. Chudzik ,  Ravikumar Ramachandran

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823842

Abstract: A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.

Abstract translation: 在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。 阻挡金属层可以直接沉积在栅极介电层上。 图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。 第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。 或者，第一类功函数层可以直接沉积在栅介电层上。 图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。 第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。 导电材料填充和平坦化形成双功能功能替代栅极结构。

公开(公告)号：US09257519B2

公开(公告)日：2016-02-09

申请号：US14081417

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Joseph F. Shepard, Jr. ,  Keith K. H. Wong

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/336 ,  H01L29/49 ,  H01L29/47 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28202 ,  H01L29/47 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底; 以及栅极结构，其直接设置在所述基板上，所述栅极结构包括：具有不同材料浓度分布的渐变区域; 以及设置在分级区域上的金属层。

公开(公告)号：US09196700B2

公开(公告)日：2015-11-24

申请号：US14640698

申请日：2015-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Barry P. Linder ,  Shahab Siddiqui

IPC: H01L21/02 ,  H01L29/51 ,  H01L27/088 ,  H01L27/12 ,  H01L21/28 ,  H01L21/324 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/513 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/2807 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/518

Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.

Abstract translation: 可以通过利用第一原子层沉积工艺沉积第一氧化硅材料来形成栅极电介质。 选择第一氧化硅材料的厚度以对应于第一原子层沉积工艺的至少10个沉积循环。 通过第一等离子体氮化工艺将第一氧化硅材料转化为第一氮氧化硅材料。 随后通过第二原子层沉积工艺沉积第二氧化硅材料。 通过第二等离子体氮化处理将第二氧化硅材料转化为第二氮氧化硅材料。 原子层沉积工艺和等离子体氮化处理的多次重复提供氮氮原子与氧原子的比率大于1/3的氮氧化硅材料，其可以有利地用于减少通过栅极电介质的漏电流。

公开(公告)号：US08835292B2

公开(公告)日：2014-09-16

申请号：US13664744

申请日：2012-10-31

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC: H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US20170236780A1

公开(公告)日：2017-08-17

申请号：US15485657

申请日：2017-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US20170213792A1

公开(公告)日：2017-07-27

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

公开(公告)号：US09627508B2

公开(公告)日：2017-04-18

申请号：US14685944

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/88 ,  H01L29/20 ,  H01L21/02 ,  H01L29/739 ,  H01L29/267

CPC classification number: H01L29/66545 ,  H01L21/02538 ,  H01L21/02617 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/88

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.