公开(公告)号：US11416730B2

公开(公告)日：2022-08-16

申请号：US16949155

申请日：2020-10-15

Applicant: Infineon Technologies AG

Inventor： Bernhard Rieder ,  Thomas Kilger

IPC: G06K19/077 ,  H01L23/66 ,  H01Q1/38 ,  H01Q1/22

Abstract: A radio-frequency device comprises a radio-frequency chip, a first connecting element arranged over a chip surface of the radio-frequency chip, the first connecting element being designed to mechanically and electrically connect the radio-frequency chip to a circuit board, and a radio-frequency signal carrying element arranged over the chip surface and electrically coupled to the radio-frequency chip, the radio-frequency signal carrying element being covered by an electrically nonconductive material and being designed to transmit a signal in a direction parallel to the chip surface, wherein the first connecting element and the radio-frequency signal carrying element are arranged at a same level in relation to a direction perpendicular to the chip surface, and wherein the first connecting element is spaced apart from the radio-frequency signal carrying element by way of a region that is free of the electrically nonconductive material.

公开(公告)号：US09806056B2

公开(公告)日：2017-10-31

申请号：US15044021

申请日：2016-02-15

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Dominic Maier ,  Thomas Kilger

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76838 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/48 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.

公开(公告)号：US20150064846A1

公开(公告)日：2015-03-05

申请号：US14535591

申请日：2014-11-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L21/56 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US20150028435A1

公开(公告)日：2015-01-29

申请号：US14454247

申请日：2014-08-07

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Dominic Maier ,  Thomas Kilger

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2201/0257 ,  H01L21/568 ,  H01L23/48 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H03H9/1064 ,  H04R19/005 ,  H01L2924/00

Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.

Abstract translation: 一种封装集成电路的方法包括：提供具有多个第一半导体管芯和多个第二半导体管芯的模制衬底，所述第二半导体管芯相互间隔开并被模制化合物覆盖。 将模塑料稀薄以暴露至少一些第二半导体管芯。 暴露的第二半导体管芯被移除以在模塑衬底中形成空腔。 多个第三半导体管芯被插入形成在模制基板中的空腔中，并且电连接形成于第一半导体管芯和第三半导体管芯。

公开(公告)号：US20140070913A1

公开(公告)日：2014-03-13

申请号：US14024395

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Urs Elrod ,  Christiane Brunner ,  Thomas Kilger

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2819 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/645 ,  H01L24/19 ,  H01L2224/12105 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.

Abstract translation: 根据实施例，变压器包括设置在第一电介质层的第一侧上的第一导电层中的第一线圈和设置在第一电介质层的第二侧上的第二导电层中的第二线圈。 每个线圈具有设置在其相应线圈内部的第一端和设置在其相应线圈的外周边的第二端。 设置在第二导电层中的第一交叉直接连接到第一线圈的第一端并且延伸超过第一线圈的外周。 此外，设置在第一导电层中的第二交叉直接连接到第二线圈的第一端并且延伸超过第二线圈的外周。

公开(公告)号：US20220148951A1

公开(公告)日：2022-05-12

申请号：US17544221

申请日：2021-12-07

Applicant: Infineon Technologies AG

Inventor： Ngoc-Hoa Huynh ,  Franz-Xaver Muehlbauer ,  Claus Waechter ,  Veronika Theyerl ,  Dominic Maier ,  Thomas Kilger ,  Saverio Trotta ,  Ashutosh Baheti ,  Georg Meyer-Berg ,  Maciej Wojnowski

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/538 ,  H01Q9/28 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

公开(公告)号：US20190221465A1

公开(公告)日：2019-07-18

申请号：US16249142

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Francesca Arcioni ,  Maciej Wojnowski

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/66 ,  H01L24/02 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/02381

Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.

公开(公告)号：US20160311679A1

公开(公告)日：2016-10-27

申请号：US15138313

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Alfons Dehe ,  Thomas Kilger ,  Markus Menath ,  Franz Xaver Muehlbauer ,  Daniel Porwol ,  Juergen Wagner

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00896 ,  B81C1/00269 ,  B81C1/00801 ,  B81C2201/0194 ,  B81C2201/053

Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.

Abstract translation: 对芯片封装的制造方法进行说明。 多个芯片设置在第一晶片上。 每个芯片具有通向芯片的第一主面的空腔。 空腔被暂时填充或覆盖。 然后将芯片分开。 单片化芯片嵌入封装材料中，然后将空腔重新曝光。

公开(公告)号：US20160035677A1

公开(公告)日：2016-02-04

申请号：US14450307

申请日：2014-08-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ulrich Wachter ,  Thomas Kilger

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3157 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A method for forming a package arrangement is provided, which may include: arranging at least one chip over a carrier; at least partially encapsulating the at least one chip with encapsulation material, wherein the encapsulation material is formed such that at least a portion of the carrier is uncovered by the encapsulation material; forming an electrically conductive structure over the encapsulation material and on the portion of the carrier uncovered by the encapsulation material; removing the carrier; and then forming a redistribution structure over the chip and the electrically conductive structure, wherein the redistribution structure electrically couples the electrically conductive structure and the chip.

Abstract translation: 提供了一种用于形成封装结构的方法，其可以包括：在载体上布置至少一个芯片; 至少部分地用封装材料封装所述至少一个芯片，其中所述封装材料形成为使得所述载体的至少一部分未被所述封装材料覆盖; 在所述封装材料和所述载体的由所述封装材料覆盖的部分上形成导电结构; 移除载体; 然后在所述芯片和所述导电结构上形成再分布结构，其中所述再分布结构电耦合所述导电结构和所述芯片。

公开(公告)号：US20160005728A1

公开(公告)日：2016-01-07

申请号：US14853808

申请日：2015-09-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01F27/29 ,  H01L23/64 ,  H01L21/3205 ,  H01L25/065 ,  H01F27/28 ,  H01L21/78 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01F27/2804 ,  H01F27/29 ,  H01F2027/2809 ,  H01L21/32051 ,  H01L21/56 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/40 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/11005 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/40227 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83801 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/165 ,  H05K1/181 ,  H05K1/185 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

Abstract translation: 公开了制造系统的系统和方法。 系统的一个实施例包括第一封装元件，其包括设置在第一封装元件的第一主表面上的第一元件和第一再分布层（RDL），其中第一RDL包括第一焊盘。 所述系统还包括具有设置在所述第二封装部件的第一主表面处的第二部件的第二封装部件，所述第一主表面具有第二焊盘和所述第一封装部件与所述第二封装部件之间的连接层，其中所述连接层 将第一多个第一焊盘与第二焊盘连接。