公开(公告)号：US09281235B2

公开(公告)日：2016-03-08

申请号：US14613154

申请日：2015-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

IPC: H01L21/768 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

公开(公告)号：US08823172B2

公开(公告)日：2014-09-02

申请号：US14175162

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwan-Sik Lim ,  Sunwon Kang ,  Jongho Lee

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05578 ,  H01L2224/0603 ,  H01L2224/06515 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.

Abstract translation: 半导体封装包括具有第一凸块组和第二凸块组的半导体芯片，以及具有用于与半导体芯片进行数据通信的第一图案的封装基板和用于向半导体芯片供电或将半导体芯片接地的第二图案， 其中所述第一凸块组设置在所述第一图案上，并且所述第二凸块组设置在所述第二图案上。

公开(公告)号：US12237240B2

公开(公告)日：2025-02-25

申请号：US17573426

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US11874026B2

公开(公告)日：2024-01-16

申请号：US17309521

申请日：2019-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungsoo Lim ,  Kyoungmok Kim ,  Seulkiro Kim ,  Sunhee Park ,  Hyesoon Yang ,  Kisup Lee ,  Sinyoung Lee ,  Jongho Lee ,  Mingyu Jung ,  Jeongsu Han

IPC: F24F8/60 ,  B01D53/02 ,  B01D53/62 ,  F24F8/15 ,  F24F8/95 ,  F24F7/08 ,  F24F7/00

CPC classification number: F24F8/60 ,  B01D53/02 ,  B01D53/62 ,  F24F7/08 ,  F24F8/15 ,  F24F8/95 ,  F24F2007/001

Abstract: Disclosed is an air conditioner for creating a comfortable indoor environment. The air conditioner includes an indoor unit configured to have a carbon dioxide remover for filtering carbon dioxide from indoor air to supply clean air into a room, and discharging the filtered carbon dioxide to the outside, an outdoor unit configured to have an oxygen generator for separating oxygen from outdoor air introduced from the outside to supply the separated oxygen into the room, and discharging residues from which the oxygen is separated to the outside; and a processor configured to control the carbon dioxide remover and the oxygen generator to discharge the filtered carbon dioxide and the residues to the outdoor together. According to the disclosure, by first removing the carbon dioxide from the room and then discharging the carbon dioxide and the residues while operating the oxygen generator, a piping installation operation by a simple piping structure as well as an efficient operation is possible.

公开(公告)号：US11587906B2

公开(公告)日：2023-02-21

申请号：US17168238

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Jongho Lee ,  Teakhoon Lee

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US11569145B2

公开(公告)日：2023-01-31

申请号：US17188332

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Juhyun Lyu ,  Unbyoung Kang ,  Chulwoo Kim ,  Jongho Lee

IPC: H01L23/36 ,  H01L23/40 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

公开(公告)号：US11222873B2

公开(公告)日：2022-01-11

申请号：US16936882

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US20210384096A1

公开(公告)日：2021-12-09

申请号：US17188332

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Juhyun Lyu ,  Unbyoung Kang ,  Chulwoo Kim ,  Jongho Lee

IPC: H01L23/36 ,  H01L25/065 ,  H01L23/40

Abstract: A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

公开(公告)号：US20210066046A1

公开(公告)日：2021-03-04

申请号：US16883392

申请日：2020-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Jaeho Kwak ,  Boeun Jang ,  Seokyeon Hwang ,  Yongseok Seo ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee ,  Jongho Lee ,  Daewook Kim ,  Wonpil Lee ,  Changkyu Choi

IPC: H01J37/32 ,  H01L21/67 ,  H01J37/34

Abstract: A surface treatment apparatus and a surface treatment system having the same are disclosed. The surface treatment apparatus includes a process chamber in which the surface treatment process is conducted, a plasma generator for generating process radicals as a plasma state for the surface treatment process, the plasma generator being positioned outside of the process chamber and connected to the process chamber by a supply duct, a heat exchanger arranged on the supply duct and cooling down temperature of the process radicals passing through the supply duct and a flow controller controlling the process radicals to flow out of the process chamber. The flow controller is connected to a discharge duct through which the process radicals are discharged outside the process chamber. The plasma surface treatment process is conducted to the package structure having minute mounting gap without the damages to the IC chip and the board.

公开(公告)号：US20170250184A1

公开(公告)日：2017-08-31

申请号：US15438113

申请日：2017-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L23/535

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.