公开(公告)号：US20080192447A1

公开(公告)日：2008-08-14

申请号：US12052087

申请日：2008-03-20

Applicant: Kunihiro KOYAMA ,  Muneyoshi YAMAMOTO ,  Takanori UEJIMA ,  Dai NAKAGAWA ,  Masaki KIMURA

Inventor： Kunihiro KOYAMA ,  Muneyoshi YAMAMOTO ,  Takanori UEJIMA ,  Dai NAKAGAWA ,  Masaki KIMURA

IPC: H05K5/00 ,  H05K3/30

CPC classification number: H01L25/165 ,  H01L23/3121 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/141 ,  H05K3/284 ,  H05K3/288 ,  H05K3/303 ,  H05K2201/0125 ,  H05K2203/0195 ,  H05K2203/082 ,  H05K2203/083 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A suction surface member is provided on an electronic component module including an electronic component base plate and surface mount device mounted on the electronic component base plate in order to provide a suction surface at a location that is substantially at the same level as or higher than that of an upper end of a transistor that is the tallest surface mount device. The suction head adheres to the suction surface to hold the electronic component module and the electronic component module is mounted on a motherboard defining the target board. Then a treatment is performed to prevent a situation in which an upper end of the suction surface member is higher than the upper end of the tallest surface mount device mounted on the electronic component base plate.

Abstract translation: 吸引面构件设置在电子部件模块上，该电子部件模块包括电子部件基板和安装在电子部件基板上的表面安装装置，以便在与基本上等于或高于 作为最高的表面安装器件的晶体管的上端。 吸头粘附到吸力表面以保持电子部件模块，电子部件模块安装在限定目标板的主板上。 然后进行处理以防止吸附表面构件的上端高于安装在电子部件基板上的最高表面安装装置的上端的情况。

公开(公告)号：US07202422B2

公开(公告)日：2007-04-10

申请号：US10511994

申请日：2003-04-23

Applicant: Toshinobu Ogatsu

Inventor： Toshinobu Ogatsu

IPC: H05K9/00

CPC classification number: H05K3/284 ,  H05K1/0218 ,  H05K9/0039 ,  H05K2201/0125 ,  H05K2201/10303 ,  H05K2203/1189 ,  H05K2203/1311

Abstract: In a method of shielding a circuit device, a circuit board on which an electronic component has mounted and which has a ground connection portion is provided. An entire portion of the circuit board is inserted into a shield pack having a sack shape. The shield pack has an insulating layer as an innermost layer and an electric conductive layer as an outermost layer. The insulating layer of the shield pack is contacted with the electronic component and the circuit board. The ground connection portion of the circuit board is connected to the electric conducive layer of the shield pack.

Abstract translation: 在屏蔽电路装置的方法中，提供了其上安装有电子部件并具有接地连接部分的电路板。 将电路板的整个部分插入具有袋形状的屏蔽包中。 屏蔽组件具有作为最内层的绝缘层和作为最外层的导电层。 屏蔽包的绝缘层与电子部件和电路板接触。 电路板的接地连接部分连接到屏蔽包的电气导电层。

公开(公告)号：US20050162841A1

公开(公告)日：2005-07-28

申请号：US10511994

申请日：2003-04-23

Applicant: Toshinobu Ogatsu

Inventor： Toshinobu Ogatsu

IPC: H05K1/02 ,  H05K3/28 ,  H05K9/00

CPC classification number: H05K3/284 ,  H05K1/0218 ,  H05K9/0039 ,  H05K2201/0125 ,  H05K2201/10303 ,  H05K2203/1189 ,  H05K2203/1311

Abstract: In a method of shielding a circuit device, a circuit board on which an electronic component has mounted and which has a ground connection portion is provided. An entire portion of the circuit board is inserted into a shield pack having a sack shape. The shield pack has an insulating layer as an innermost layer and an electric conductive layer as an outermost layer. The insulating layer of the shield pack is contacted with the electronic component and the circuit board. The ground connection portion of the circuit board is connected to the electric conducive layer of the shield pack.

Abstract translation: 在屏蔽电路装置的方法中，提供了其上安装有电子部件并具有接地连接部分的电路板。 将电路板的整个部分插入具有袋形状的屏蔽包中。 屏蔽组件具有作为最内层的绝缘层和作为最外层的导电层。 屏蔽包的绝缘层与电子部件和电路板接触。 电路板的接地连接部分连接到屏蔽包的电气导电层。

公开(公告)号：US20050142835A1

公开(公告)日：2005-06-30

申请号：US11068676

申请日：2005-03-01

Applicant: Michael Ball ,  Chad Cobbley

Inventor： Michael Ball ,  Chad Cobbley

IPC: H01L21/60 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H01L21/44

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/0041 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/0125 ,  H05K2201/0191 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of forming conductive structures on the contact pads of a substrate, such as a semiconductor die or a printed circuit board. A solder mask is secured to an active surface of the substrate. Apertures through the solder mask are aligned with contact pads on the substrate. The apertures may be preformed or formed after a layer of the material of which the solder mask is comprised has been disposed on the substrate. Conductive material is disposed in and shaped by the apertures of the solder mask to form conductive structures in communication with the contact pads exposed to the apertures. Sides of the conductive structures are exposed through the solder mask, either by removing the solder mask from the substrate or by reducing the thickness of the solder mask. The present invention also includes semiconductor devices formed during different stages of the method of the present invention.

Abstract translation: 在诸如半导体管芯或印刷电路板的衬底的接触焊盘上形成导电结构的方法。 焊接掩模固定到基板的有效表面。 通过焊接掩模的孔径与衬底上的接触焊盘对准。 可以在其包含焊料掩模的材料层已经布置在基底上之后预先形成或形成孔。 导电材料设置在焊接掩模的孔中并由其形成，以形成与暴露于孔的接触焊盘相连通的导电结构。 通过焊接掩模暴露出导电结构的侧面，通过从衬底去除焊接掩模或通过减小焊接掩模的厚度。 本发明还包括在本发明方法的不同阶段形成的半导体器件。

公开(公告)号：US20040020031A1

公开(公告)日：2004-02-05

申请号：US10207988

申请日：2002-07-31

Inventor： Tien-Min Lu

IPC: H01H011/02 ,  H03M011/00 ,  H05K003/34

CPC classification number: H05K3/12 ,  H01H2209/002 ,  H01H2217/012 ,  H01H2229/002 ,  H01H2229/004 ,  H01H2229/036 ,  H01H2229/038 ,  H01H2229/05 ,  H05K1/0393 ,  H05K2201/0125 ,  H05K2201/0145 ,  H05K2203/1105 ,  Y10T29/49105 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/4987

Abstract: A method for manufacturing membranes after having defined the button key position circuit and matrix layout under the conditions of without jumping and without generating ghost keys includes the steps of: heating and pre-shrinking the PET of a membrane, printing a circuit made from silver paste on the membrane, printing an insulation layer on the printed silver paste circuit or printing carbon powders, folding the membrane and welding the membrane by supersonic wave, and finally punching structural holes on the membrane to complete the membrane production.

Abstract translation: 一种在没有跳跃而不产生重影键的情况下定义了按钮键位置电路和矩阵布局之后制造膜的方法包括以下步骤：加热和预收缩膜的PET，印刷由银糊制成的电路 在膜上，在印刷银浆电路上印刷绝缘层或印刷碳粉，折叠膜并通过超声波焊接膜，最后在膜上冲孔结构孔以完成膜生产。

公开(公告)号：US06001489A

公开(公告)日：1999-12-14

申请号：US998388

申请日：1997-12-24

Applicant: Chiharu Miyaake ,  Yosuke Miki ,  Toshihiko Sugimoto

Inventor： Chiharu Miyaake ,  Yosuke Miki ,  Toshihiko Sugimoto

IPC: H05K1/02 ,  B32B15/08 ,  C08J5/18 ,  H05K1/00 ,  H05K1/03 ,  H05K3/28

CPC classification number: H05K1/028 ,  B32B15/08 ,  C08J5/18 ,  C08J2367/02 ,  C08J2379/08 ,  H05K2201/0125 ,  H05K2203/0285 ,  H05K2203/102 ,  H05K3/281 ,  Y10S428/901 ,  Y10T428/31529 ,  Y10T428/31681

Abstract: A flexible printed circuit comprising a plastic film and a conducting layer, wherein the plastic film exhibits a heat shrinkage rate ellipse having an eccentricity of not more than 0.7 and preferably exhibits an ultrasonic wave propagation rate ellipse having an eccentricity of not more than 0.4 and a polarized microwave transmission intensity ellipse having an eccentricity of not more than 0.55. The flexible printed circuit has improved dimensional accuracy owing to the dimensional stability of the plastic film.

Abstract translation: 一种柔性印刷电路，包括塑料膜和导电层，其中所述塑料膜呈现偏心率不大于0.7的热收缩率椭圆，并且优选地具有偏心率不大于0.4的超声波传播速率椭圆，以及 偏振微波透射强度椭圆偏心率不大于0.55。 由于塑料膜的尺寸稳定性，柔性印刷电路具有改善的尺寸精度。

公开(公告)号：US5531020A

公开(公告)日：1996-07-02

申请号：US112225

申请日：1993-08-27

Applicant: David Durand ,  Roger A. Iannetta, Jr.

Inventor： David Durand ,  Roger A. Iannetta, Jr.

IPC: C09J163/00 ,  H01B1/22 ,  H01L21/48 ,  H01L21/60 ,  H01R4/04 ,  H05K1/09 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/28 ,  H05K3/32 ,  H05K3/34

CPC classification number: H01L24/83 ,  C09J163/00 ,  H01B1/22 ,  H01L21/4867 ,  H01L24/29 ,  H01L24/81 ,  H01R4/04 ,  H05K3/1258 ,  H05K3/321 ,  H01L2224/13111 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/3025 ,  H05K1/095 ,  H05K1/181 ,  H05K2201/0125 ,  H05K2201/0218 ,  H05K2201/023 ,  H05K2201/0245 ,  H05K2201/0272 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2203/0307 ,  H05K2203/0568 ,  H05K2203/1105 ,  H05K2203/1453 ,  H05K3/0023 ,  H05K3/107 ,  H05K3/28 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: A method of making a planar, subsurface electronic circuit having at least one electronic circuit component assembled therewith is disclosed. First, three dimensional, essentially square channels interspersed with lands are formed within a dielectric material on a substrate. The channels are then filled in one pass with a curable polymeric material containing a conductive metal filler so that the upper surfaces of the circuit trace formed by this conductive material are at essentially the same level as the upper surface of the lands. Circuit components are place to engage the conductive material. The curable material is then cured after placing the electronic component(s).

Abstract translation: 公开了一种制造具有组装的至少一个电子电路部件的平面的地下电子电路的方法。 首先，在衬底上的电介质材料内形成散布有焊盘的三维，基本上为方形的通道。 然后将通道用含有导电金属填料的可固化聚合物材料一次填充，使得由该导电材料形成的电路迹线的上表面基本上与焊盘的上表面相同。 电路元件是与导电材料接合的地方。 然后在放置电子部件之后固化可固化材料。

公开(公告)号：US5180523A

公开(公告)日：1993-01-19

申请号：US436199

申请日：1989-11-14

Applicant: David Durand ,  David P. Vieau ,  Ang-Ling Chu ,  Tai S. Weiu

Inventor： David Durand ,  David P. Vieau ,  Ang-Ling Chu ,  Tai S. Weiu

IPC: C09J163/00 ,  H01B1/22 ,  H01R4/04 ,  H05K1/18 ,  H05K3/00 ,  H05K3/32

CPC classification number: H05K3/321 ,  C09J163/00 ,  H01B1/22 ,  H01R4/04 ,  H05K1/181 ,  H05K2201/0125 ,  H05K2201/0218 ,  H05K2201/023 ,  H05K2201/0245 ,  H05K2201/0272 ,  H05K2203/0307 ,  H05K2203/0568 ,  H05K2203/1105 ,  H05K2203/1453 ,  H05K3/0023 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/25

Abstract: An electrically conductive cement having substantially stable conductivity and resistance characteristics under high humidity conditions comprises a mixture of two epoxy resins with the proportion of each epoxy resin adjusted to provide a volumetric shrinkage in the mixture in the 4 to 16% and a conductive silver particular filler including agglomerates having size and surface characteristics that maintain stable electrical contact with an electrical component lead. The epoxy mixture is preferably a combination of a high-shrinkage epoxy resin and a lower-shrinkage epoxy resin in the appropriate amounts of each so as to produce the desired volumetric shrinkage characteristic. The conductive particle filler is preferably an admixture of silver flakes, silver powder, and an effective amount of silver agglomerates. The agglomerates are irregularly shaped particles having multiple surface indentations and recesses to produce many rough-edged salients or ridges and having a particle length, width, and thickness aspect ratio of about 1:1:1. An effective amount of such agglomerates appears to effect penetration of surface oxides when establishing the cemented connection as a result of the volumetric shrinkage of the polymeric carrier upon curing.

Abstract translation: 在高湿度条件下具有基本上稳定的导电性和电阻特性的导电水泥包括两种环氧树脂的混合物，其中每种环氧树脂的比例被调节以提供4至16％的混合物的体积收缩率和导电的银特殊填料 包括具有与电气部件引线保持稳定的电接触的尺寸和表面特性的附聚物。 环氧混合物优选为高收缩率环氧树脂和较低收缩率的环氧树脂的组合，以适当的量，以产生所需的体积收缩特性。 导电颗粒填料优选为银薄片，银粉和有效量的银附聚物的混合物。 附聚物是具有多个表面凹陷和凹陷的不规则形状的颗粒，以产生许多粗边缘的凸起，并且具有约1:1:1的颗粒长度，宽度和厚度纵横比。 当固化时聚合物载体的体积收缩结果确定粘合连接时，有效量的这种附聚物似乎会影响表面氧化物的渗透。

公开(公告)号：US10349530B1

公开(公告)日：2019-07-09

申请号：US15863668

申请日：2018-01-05

Applicant: HAMILTON SUNDSTRAND CORPORATION

Inventor： Robert C. Cooney ,  John Huss ,  Kandy Elaine Spahr ,  Deron J. Staas ,  Mark W. Metzler ,  Debabrata Pal

IPC: H05K7/00 ,  H05K3/28 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K3/285 ,  H05K1/181 ,  H05K3/0044 ,  H05K3/284 ,  H05K2201/0108 ,  H05K2201/0125 ,  H05K2201/0129 ,  H05K2203/1333

Abstract: A system for protecting electronics includes a printed wiring assembly (PWA) having a surface with at least one electronic component. The system also includes a water resistant film configured to be used as a conformal coating on the PWA and further configured to be placed on the surface of the PWA and to shrink about the at least one electronic component.

公开(公告)号：US09832875B2

公开(公告)日：2017-11-28

申请号：US14333856

申请日：2014-07-17

Applicant: Hamilton Sundstrand Corporation

Inventor： Slade R. Culp ,  Sameh Dardona ,  Wayde R. Schmidt

IPC: H05K1/16 ,  C23C18/16 ,  B32B37/06 ,  H05K3/12 ,  H05K3/36 ,  H05K1/02 ,  H05K1/09 ,  H05K3/46

CPC classification number: H05K1/16 ,  B32B37/06 ,  B32B2305/72 ,  C23C18/1633 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/165 ,  H05K3/12 ,  H05K3/36 ,  H05K3/4617 ,  H05K2201/0125 ,  H05K2201/0129 ,  H05K2203/06 ,  H05K2203/1105

Abstract: A method for fabricating printed electronics includes printing a trace of an electrical component on a first substrate to form a first layer. The method further includes printing a trace of an electrical component on at least one additional substrate to form at least one additional layer. The first layer is stacked with the at least one additional layer to create an assembled electrical device. At least one of the layers is modified after printing.