公开(公告)号：US4970577A

公开(公告)日：1990-11-13

申请号：US337145

申请日：1989-04-12

Applicant: Satoru Ogihara ,  Shunichi Numata ,  Kunio Miyazaki ,  Takashi Yokoyama ,  Ken Takahashi ,  Tasao Soga ,  Kazuji Yamada ,  Hiroichi Shinohara ,  Hideo Suzuki

Inventor： Satoru Ogihara ,  Shunichi Numata ,  Kunio Miyazaki ,  Takashi Yokoyama ,  Ken Takahashi ,  Tasao Soga ,  Kazuji Yamada ,  Hiroichi Shinohara ,  Hideo Suzuki

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/52 ,  H01L23/64 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H01L23/642 ,  H01L23/49827 ,  H01L23/49833 ,  H05K1/141 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K1/0271 ,  H05K1/0306 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K3/3426 ,  H05K3/368

Abstract: A semiconductor chip module includes semiconductor chips each of which has contacts on its entire front face. A multi-layered organic circuit board having a small dielectric constant is provided for mounting the semiconductor chips. Intermediate ceramic substrates having the same thermal expansion coefficient as that of the semiconductor chip, are also provided. Each such intermediate ceramic substrate has contacts on its front and back faces corresponding to those of the semiconductor chip. These contacts are electrically connected directly in a one-to-one relationship. The contacts on the semiconductor chip and the corresponding ones on the front face of the intermediate ceramic substrates are connected by solder. The contacts on the back face of the intermediate ceramic substrate and the corresponding contacts on the front face of the multi-layered ceramic circuit board are connected by respective conductive pins having a predetermined flexibility and rigidity through a predetermined gap therebetween. With this arrangement, the relative displacement due to a thermal expansion difference between the intermediate ceramic substrate and the multi-layered organic circuit board is permitted without causing substantial stress thereon.

公开(公告)号：US4787853A

公开(公告)日：1988-11-29

申请号：US30505

申请日：1987-03-27

Applicant: Yutaka Igarashi

Inventor： Yutaka Igarashi

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K3/42 ,  H05K1/00

CPC classification number: H05K1/111 ,  H05K1/112 ,  H05K3/308 ,  H05K3/3421 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/10704 ,  H05K2201/10871 ,  H05K2201/10901 ,  H05K2203/0455 ,  H05K3/321 ,  H05K3/42 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed circuit board is disclosed which comprises a plurality of non-through holes into thickness direction in one surface of the board, a plurality of through holes in some of the non-through holes to open through opposite surface of the board and having a smaller inside diameter than the non-through holes, a plurality of first conductive lands on the periphery of the openings of the non-through holes in one surface of the board, a plurality of second conductive lands on the periphery of the openings in opposite surface of the through holes and having the smaller outside diameter than the second lands on the periphery of the openings of the non-through holes, a conductor layer in inside wall of the non-through holes and the through holes for connecting the first lands in one surface and the second conductive lands in opposite surface of board, and conductive patterns formed in one surface and opposite surface of the board respectively, which invention is capable of including the great number of the conductive patterns as necessary for mounting the electric component such as PGA or HPC without multilayering the board or going around of the conductive patterns, because of the greater number of the spaces between the second lands can be formed in opposite surface.

Abstract translation: 公开了一种印刷电路板，其包括在板的一个表面中的厚度方向上的多个非通孔，一些非通孔中的多个通孔，通过板的相对表面打开并具有较小的 在所述板的一个表面中的所述非通孔的开口周边上的多个第一导电焊盘，所述多个第一导电焊盘在所述板的一个表面中的所述开口的周边上， 所述通孔具有比所述非通孔的开口周边上的第二焊盘小的外径，所述非通孔的内壁中的导体层和用于将一个表面中的第一焊盘连接的通孔 并且板的相对表面中的第二导电焊盘和分别形成在板的一个表面和相对表面中的导电图案，其能够包括gr 由于可以在相对的表面上形成第二焊盘之间的更大数量的空间，因此可以根据需要安装诸如PGA或HPC的电气部件的数量的导电图案，而不需要多层导电板或导电图案。

公开(公告)号：US4709302A

公开(公告)日：1987-11-24

申请号：US942097

申请日：1986-12-16

Applicant: William D. Jordan ,  Donald L. Clemens

Inventor： William D. Jordan ,  Donald L. Clemens

IPC: H01L23/32 ,  H05K1/18 ,  H05K3/30 ,  H05K7/12 ,  H05K7/20

CPC classification number: H05K3/306 ,  H01R12/7005 ,  H05K7/12 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10863 ,  H05K3/301

Abstract: Disclosed is apparatus for mounting electronic device packages and heat sinks on printed circuit boards with the pin connectors of the electronic device package held in alignment with preformed locations on the printed circuit boards. The alignment apparatus includes means for securing the electronic device package in intimate thermal contact with the heat sink for rapid dissipation of heat therefrom.

Abstract translation: 公开了用于将电子设备封装和散热器安装在印刷电路板上的装置，其中电子器件封装的引脚连接器与印刷电路板上的预先形成的位置保持一致。 对准装置包括用于固定电子装置包装件与散热器紧密热接触的装置，用于从其快速散发热量。

公开(公告)号：US4661887A

公开(公告)日：1987-04-28

申请号：US793414

申请日：1985-10-31

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/50 ,  H05K1/18 ,  H05K3/34 ,  H05K13/04 ,  H01R9/09

CPC classification number: H05K3/3426 ,  H05K13/0465 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/1084 ,  H05K2201/10984 ,  Y02P70/613 ,  Y10T29/49144

Abstract: An integrated circuit package having a plurality of leads capable of holding a quantity of solder paste prior to bonding to a printed circuit board or other substrate. The solder paste bearing structure may be straight or spiral grooves, or even a slot or roughened surface, running down at least the lower length of the leads as long as some mechanism is present which will first hold the solder paste or other electrically conductive binder on the lead and then deliver the binder to the end of the lead to produce an electrical and structural bond in a binder flowing operation. Application of the solder paste to the leads is accomplished by simply dipping the package leads into the paste thereby eliminating the need to make a solder mask for the substrate as well as the task of aligning the mask to the substrate.

Abstract translation: 一种集成电路封装，其具有多个引线，其能够在与印刷电路板或其它基板接合之前保持一定量的焊膏。 焊膏支承结构可以是直的或螺旋形的沟槽，或者甚至是槽或粗糙表面，只要存在一些将首先将焊膏或其它导电粘合剂保持在其上的机构，至少沿着引线的较低长度向下延伸 引线，然后将粘合剂输送到引线的末端，以在粘合剂流动操作中产生电和结构粘合。 通过将封装引线简单地浸入糊料中，可以将焊膏施加到引线上，从而不需要为衬底制造焊接掩模以及将掩模对准衬底的任务。

公开(公告)号：US4530002A

公开(公告)日：1985-07-16

申请号：US391161

申请日：1982-06-22

Applicant: Yasunori Kanai

Inventor： Yasunori Kanai

IPC: H05K1/18 ,  H01L23/055 ,  H01L23/057 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H05K3/34 ,  H01L23/48

CPC classification number: H05K3/3415 ,  H01L23/055 ,  H01L23/057 ,  H01L23/49827 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/30107 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K3/3421 ,  H05K3/3447 ,  Y02P70/613

Abstract: A semiconductor device having improved construction of connection leads extending from the chip carrier housing for connecting a semiconductor chip in the housing with the external circuitry. The connection leads are arranged in the form of a plurality of concentric arrays. The leads in the outermost array are composed of surface connection leads to be electrically connected to the uppermost layer of a multilayer printed board to which the semiconductor device will be mounted, and the leads in the inner array or arrays are composed of lead pins to be inserted into and be electrically connected to the through holes of the multilayer printed board.

Abstract translation: 一种半导体器件，其具有从芯片载体壳体延伸的连接引线的改进结构，用于将壳体中的半导体芯片与外部电路连接。 连接引线以多个同心圆盘的形式布置。 最外面阵列中的引线由表面连接引线组成，电连接到多层印刷电路板的最上层，半导体器件将被安装到其上，内部阵列或阵列中的引线由引脚引脚组成 插入并电连接到多层印刷电路板的通孔。

公开(公告)号：US3331912A

公开(公告)日：1967-07-18

申请号：US3331912D

IPC: H05K3/30 ,  H05K3/34

CPC classification number: H05K3/308 ,  H05K3/3447 ,  H05K2201/10568 ,  H05K2201/10704 ,  H05K2201/10871 ,  H05K2201/2036 ,  Y10T29/49149

公开(公告)号：US12002795B2

公开(公告)日：2024-06-04

申请号：US17719857

申请日：2022-04-13

Applicant: Google LLC

Inventor： Houle Gan ,  Richard Stuart Roy ,  Yujeong Shim ,  William F. Edwards, Jr. ,  Chenhao Nan

IPC: H05K1/11 ,  H01L25/16 ,  H05K1/18 ,  H01L23/00

CPC classification number: H01L25/162 ,  H05K1/11 ,  H05K1/183 ,  H01L24/16 ,  H01L2224/16225 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10166 ,  H05K2201/1053 ,  H05K2201/10704 ,  H05K2201/10719

Abstract: A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contacts that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board. An assembly includes the pluggable processor module and a printed circuit board assembly (“PCBA”) including a module aperture that is large enough to receive the power board and narrower than the capacitor board.

公开(公告)号：US20230380067A1

公开(公告)日：2023-11-23

申请号：US17750016

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Kai Xiao ,  Carlos Alberto Lizalde Moreno ,  Luis E. Rosales Galvan

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H05K2201/10325 ,  H05K2201/10303 ,  H05K2201/10704

Abstract: In one embodiment, a package substrate or main circuit board includes electrical connectors arranged in a compressed array pattern, wherein a distance between a connector and its neighboring connectors in a direction of compression is less than a distance between the connector and its neighboring connectors in other directions. The array pattern may be hexagonal or rectangular, and differential pairs of the electrical connectors may be arranged in the direction of compression.

公开(公告)号：US11751339B2

公开(公告)日：2023-09-05

申请号：US17449032

申请日：2021-09-27

Applicant: GLOBAL MASTER TECH. CO., LTD.

Inventor： Yao-Hua Kao ,  Chieh-Chien Chen

IPC: H05K1/02 ,  H05K3/34 ,  H05K1/11 ,  B23K1/00 ,  B23K101/42

CPC classification number: H05K3/3447 ,  B23K1/0016 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  B23K2101/42 ,  H05K2201/096 ,  H05K2201/09545 ,  H05K2201/10704

Abstract: An electronic-component carrier board includes carrier plates formed in a stack, and insulating layers each disposed between two adjacent ones of the carrier plates. Multiple conductive pins extend through the insulating layers and the carrier plates. Multiple conductive wires equal in length and width are provided. Each conductive wire is connected to one of the conductive pins, covered by one of the insulating layers, disposed between two adjacent ones of the carrier plates, and extends outwardly from the stack of the carrier plates. A wiring method for the electronic-component carrier board is also disclosed.

公开(公告)号：US20230269868A1

公开(公告)日：2023-08-24

申请号：US18307195

申请日：2023-04-26

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tomomi NONAKA

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/36 ,  H01L25/07 ,  H01L23/00 ,  H01L23/498

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49844 ,  H01L24/32 ,  H01L25/072 ,  H05K1/145 ,  H05K3/368 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2924/15322 ,  H05K2201/042 ,  H05K2201/10166 ,  H05K2201/10704

Abstract: A semiconductor device includes a semiconductor chip with an electrode, an insulated circuit board including an insulating board and a circuit pattern formed thereon. The circuit pattern has the semiconductor chip on a front surface thereof. The semiconductor device further includes a plurality of conductive posts, each having a lower end bonded to at least one of the front surface of the circuit pattern or the electrode of the semiconductor chip, and each extending vertically upward with respect to a front surface of the insulated circuit board, a printed circuit board bonded to an upper end side of each conductive post, a spacer disposed between the printed circuit board and the insulated circuit board such that a front surface of the printed circuit board faces the insulated circuit board, and a pressing member disposed above the spacer having the printed circuit board therebetween.