公开(公告)号：US07402085B2

公开(公告)日：2008-07-22

申请号：US11402250

申请日：2006-04-11

Applicant: Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

Inventor： Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R13/6658 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes first and second conductive layers separated by a relatively thin dielectric layer. The first and second conductive layers include a crosstalk compensation arrangement having spaced-apart capacitor members. The relatively thin dielectric layer allows a high level of capacitance to be generated between the capacitor members.

Abstract translation: 本公开涉及一种电信插孔，其包括具有用于接收插头的端口的壳体。 千斤顶还包括多个接触弹簧，其适于当插头插入壳体的端口时与插头电接触，以及多个用于将插线端接到插座的导线终端触头。 千斤顶还包括将接触弹簧电连接到导线终端触点的电路板。 电路板包括由相对薄的电介质层分开的第一和第二导电层。 第一和第二导电层包括具有间隔开的电容器构件的串扰补偿装置。 相对薄的电介质层允许在电容器构件之间产生高电平的电容。

公开(公告)号：US20080020652A1

公开(公告)日：2008-01-24

申请号：US11833686

申请日：2007-08-03

Applicant: Jack Caveney ,  Masud Bolouri-Saransar ,  Scott Lesniak

Inventor： Jack Caveney ,  Masud Bolouri-Saransar ,  Scott Lesniak

IPC: H01R24/00

CPC classification number: H01R24/64 ,  H01R4/2429 ,  H01R4/2433 ,  H01R12/592 ,  H01R12/62 ,  H01R12/675 ,  H01R12/775 ,  H01R13/46 ,  H01R13/502 ,  H01R13/6461 ,  H01R13/6466 ,  H01R13/6467 ,  H01R13/6658 ,  H01R13/719 ,  H01R24/62 ,  H01R2107/00 ,  H01R2201/04 ,  H05K1/0228 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49174 ,  Y10T29/49222

Abstract: An apparatus and method for crosstalk compensation in a jack of a modular communications connector includes a flexible printed circuit board connected to jack contacts and to connections to a network cable. The flexible printed circuit board includes conductive traces arranged as one or more couplings to provide crosstalk compensation.

Abstract translation: 用于模块化通信连接器的插座中的串扰补偿的装置和方法包括连接到插座触点和连接到网络电缆的柔性印刷电路板。 柔性印刷电路板包括布置成一个或多个耦合以提供串扰补偿的导电迹线。

公开(公告)号：US20080001517A1

公开(公告)日：2008-01-03

申请号：US11767877

申请日：2007-06-25

Applicant: MASAFUMI MORIYA ,  KAZUYA ISHIWATA ,  HIROAKI TOSHIMA

Inventor： MASAFUMI MORIYA ,  KAZUYA ISHIWATA ,  HIROAKI TOSHIMA

IPC: H01J1/62 ,  H05K1/00

CPC classification number: H05K3/4685 ,  H01J17/04 ,  H01J29/04 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/09245 ,  H05K2201/10287 ,  H05K2203/0315

Abstract: To provide an electron source including: a wiring board having: a substrate provided with a groove on its surface; a first conductive member which is arranged along the groove in the groove; and a second conductive member which is arranged above the first conductive member crossing the first conductive member; and an electron-emitting device which is arranged on the wiring board and is electrically connected to the first conductive member and the second conductive member; wherein a particle is arranged between the first conductive member and an inner wall of the groove.

Abstract translation: 提供一种电子源，包括：布线板，其具有：在其表面上设置有沟槽的基板; 第一导电构件，沿着沟槽中的凹槽布置; 以及第二导电构件，其布置在与所述第一导电构件交叉的所述第一导电构件的上方; 以及电子发射器件，其布置在所述布线板上并电连接到所述第一导电部件和所述第二导电部件; 其中，所述第一导电构件和所述凹槽的内壁之间布置有颗粒。

公开(公告)号：US20070190863A1

公开(公告)日：2007-08-16

申请号：US11674359

申请日：2007-02-13

Applicant: Jack Caveney ,  Masud Bolouri-Saransar

Inventor： Jack Caveney ,  Masud Bolouri-Saransar

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R13/7195 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/189 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A jack with a flexible printed circuit board (FPC) is provided. The FPC is connected to the plug interface contacts and has a compensation circuit to compensate for near-end crosstalk (NEXT) and far-end crosstalk (FEXT). Capacitive and inductive compensation in the compensation circuit are of opposite polarity and are substantially equal in magnitude. The compensation circuit has a FEXT compensation zone containing compensation for the FEXT. Inductive and capacitive compensation in the FEXT compensation zone are distributed.

Abstract translation: 提供具有柔性印刷电路板（FPC）的插座。 FPC连接到插头接口触点，并具有补偿电路以补偿近端串扰（NEXT）和远端串扰（FEXT）。 补偿电路中的电容和电感补偿极性相反，且幅度基本相等。 补偿电路具有FEXT补偿区域，其中包含FEXT的补偿。 分布式FEXT补偿区域的感性和电容补偿。

公开(公告)号：US20070057366A1

公开(公告)日：2007-03-15

申请号：US11521156

申请日：2006-09-14

Applicant: Masashi Katsumata ,  Kenichi Kawabata ,  Toshikazu Endo

Inventor： Masashi Katsumata ,  Kenichi Kawabata ,  Toshikazu Endo

IPC: H01L23/34

CPC classification number: H01L25/18 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/24137 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0298 ,  H05K1/0373 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/0715 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09618 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10674

Abstract: A semiconductor IC-embedded module 100 comprises a multilayer substrate 101 having first and second insulating layers 101a and 101b, and a controller IC 012 and memory IC 103 that are embedded in the multilayer substrate 101. A wiring layer 104 is formed as an internal layer in the multilayer substrate 101. Part of the wiring layer 104 constitutes a bus line 104X. The controller IC 102 or memory IC 103 is embedded in the second insulating layer 101b. First and second ground layers 105a and 105b are provided respectively in the first and second insulating layers 101a and 101b. The effect of noise generated by bus lines is reduced, and an additional reduction in noise and a decrease in size and thickness are achieved by laying out bus lines that connect the semiconductor ICs so that distances are minimized.

Abstract translation: 半导体IC嵌入式模块100包括具有嵌入在多层基板101中的第一绝缘层101a和第二绝缘层101b以及控制器IC 012和存储器IC 103的多层基板101。 在多层基板101中形成布线层104作为内层。 布线层104的一部分构成总线104 X.控制器IC 102或存储器IC 103嵌入第二绝缘层101b中。 第一和第二接地层105a和105b分别设置在第一和第二绝缘层101a和101b中。 由总线产生的噪声的影响减小，通过布置连接半导体IC的总线，使距离最小化，可以实现额外的噪声降低和尺寸和厚度的减小。

公开(公告)号：US07124504B2

公开(公告)日：2006-10-24

申请号：US10450527

申请日：2002-01-11

Applicant: Ernst Steiner ,  Dieter Stroh ,  Horst Dieterle

Inventor： Ernst Steiner ,  Dieter Stroh ,  Horst Dieterle

IPC: H01R43/20 ,  H01R43/00 ,  H01R43/02 ,  H01R9/00 ,  B29C65/08 ,  B23K1/06 ,  B23K20/10

CPC classification number: B29C65/082 ,  B23K20/10 ,  B23K20/106 ,  B23K2101/38 ,  B29C66/1122 ,  B29C66/43 ,  H01R4/021 ,  H01R12/59 ,  H01R43/0207 ,  H01R43/0228 ,  H01R43/0263 ,  H05K3/328 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2203/0195 ,  H05K2203/0285 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49194 ,  Y10T29/49208 ,  Y10T29/53217 ,  Y10T29/53243

Abstract: A method and device for making multiple connections between electrical conductors surrounded by external insulators in overlapping flexible cables by ultrasonic welding. Overlapping conductors to be connected are arranged on a surface of a carrier disposed between a sonotrode and an electrode, the sonotrode and electrode are sequentially aligned the with overlapping points to be welded, and the conductors are ultrasonically welded at each of the overlapping points. The carrier either includes the electrode at least in designated areas, or includes penetrations constructed and arranged to receive an electrode in designated areas.

Abstract translation: 一种用于通过超声波焊接在由重叠的柔性电缆中被外部绝缘体包围的电导体之间进行多个连接的方法和装置。 要连接的重叠导体布置在布置在超声焊丝和电极之间的载体的表面上，超声焊丝和电极与要焊接的重叠点依次对准，并且导体在每个重叠点被超声波焊接。 载体至少在指定区域中包括电极，或包括构造和布置为在指定区域中接收电极的穿透。

公开(公告)号：US20060109062A1

公开(公告)日：2006-05-25

申请号：US11329202

申请日：2006-01-11

Applicant: Ryszard Vogel

Inventor： Ryszard Vogel

IPC: H01P5/18

CPC classification number: H05K1/0228 ,  H01P5/187 ,  H05K1/0237 ,  H05K1/162 ,  H05K2201/09245

Abstract: The invention relates to a high frequency component of layered structure, and a method for manufacturing the component. The component comprises at least one dielectric layer parallel to the layers of the layered structure, at least two transmission lines for transmitting electrical signals, at least one capacitor, each of which is formed by overlapping parts of two transmission lines, the overlapping parts being for forming capacitive interaction between the parts, and the overlapping parts being arranged to overlap each other in a transversal direction to a dielectric layer parallel to the layers of the layered structure, the dielectric layer being in between the overlapping parts.

公开(公告)号：US06937480B2

公开(公告)日：2005-08-30

申请号：US10142203

申请日：2002-05-10

Applicant: Daisuke Iguchi ,  Joji Wakita ,  Kazumi Ikeda ,  Osamu Ueno

Inventor： Daisuke Iguchi ,  Joji Wakita ,  Kazumi Ikeda ,  Osamu Ueno

IPC: H05K1/00 ,  H05K1/02 ,  H05K9/00 ,  H05K7/06

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/09254 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/10689

Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.

Abstract translation: 提供了一种印刷电路板，其可以甚至应用于高速操作的电路板，并且可以抑制电磁波辐射，并且可以抑制安装密度的劣化。 在印刷电路板上层叠有第一信号线层，具有第一电源线的第一接地层，具有第二电源线的第二接地层和第二信号线层。 第一接地层和第二接地层通过许多通孔进行层间连接。 流过信号线的信号电流的返回电流在第一接地层中流动，并且在第一电源线的位置处，中途返回电流的路径被切断。 然而，返回电流被通孔旋转到第二接地层，并在那里流动。

公开(公告)号：US20050011676A1

公开(公告)日：2005-01-20

申请号：US10621925

申请日：2003-07-17

Applicant: Andrew Barr ,  Dale Shidla ,  Robert Dobbs

Inventor： Andrew Barr ,  Dale Shidla ,  Robert Dobbs

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/0373 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09781 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A printed circuit board comprises a first conductive plane and a second conductive plane substantially parallel to the first conductive plane. The printed circuit board comprises a via signal barrel transecting the first and second conductive planes and a first anti-pad positioned between the first conductive plane and the via signal barrel. The first anti-pad has a first voided area. The printed circuit board comprises a second anti-pad positioned between the second conductive plane and the via signal barrel. The second anti-pad has a second voided area. The first voided area does not completely overlap the second voided area.

Abstract translation: 印刷电路板包括基本上平行于第一导电平面的第一导电平面和第二导电平面。 印刷电路板包括横穿第一和第二导电平面的通孔信号筒和位于第一导电平面和通孔信号筒之间的第一防焊盘。 第一个防磨垫具有第一个无效区域。 印刷电路板包括位于第二导电平面和通孔信号筒之间的第二防焊垫。 第二个防磨垫具有第二个无效区域。 第一排空区域不完全与第二空隙区域重叠。

公开(公告)号：US20040256149A1

公开(公告)日：2004-12-23

申请号：US10605324

申请日：2003-09-23

Inventor： Chi-Kung Kuan ,  Chao-Cheng Lee ,  Kuan-Hua Lee

IPC: H05K007/06

CPC classification number: H05K1/0245 ,  H05K1/115 ,  H05K2201/09245 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A symmetric electrical connection system for balancing impedance between a first node and a third node and impedance between a second node and a fourth node. The system includes a first conducting wire, a third conducting wire, a fifth conducting wire, and a seventh conducting wire all installed in a first layer. The system further includes a second conducting wire, a fourth conducting wire, a sixth conducting wire, and an eighth conducting wire all installed in a second layer. The first conducting wire and the eighth conducting wire are crossed but electrically insulated. The second conducting wire and the third conducting wire are crossed but electrically insulated. The fourth conducting wire and the fifth conducting wire are crossed but electrically insulated. The sixth conducting wire and the seventh conducting wire are crossed but electrically insulated. In a preferred embodiment, the appearances and the materials of the conducting wires are essentially equivalent.

Abstract translation: 一种用于平衡第一节点和第三节点之间的阻抗的对称电连接系统以及第二节点和第四节点之间的阻抗。 该系统包括全部安装在第一层中的第一导线，第三导线，第五导线和第七导线。 该系统还包括全部安装在第二层中的第二导线，第四导线，第六导线和第八导线。 第一导线和第八导线交叉但电绝缘。 第二导线和第三导线是交叉但电绝缘的。 第四导线和第五导线交叉但电绝缘。 第六导线和第七导线交叉但电绝缘。 在优选实施例中，导线的外观和材料基本相同。