公开(公告)号：US20010026444A1

公开(公告)日：2001-10-04

申请号：US09765413

申请日：2001-01-22

Inventor： Naoki Matsushima ,  Eiji Matsuzaki ,  Hidetaka Shigi ,  Yasunori Narizuka ,  Tetsuya Yamazaki ,  Kazuhiko Horikoshi ,  Yoichi Abe ,  Shosaku Ishihara ,  Kiyoshi Ogata ,  Toshiyuki Arai

IPC: H05K001/16

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0113 ,  H05K2203/016 ,  H05K2203/0338

Abstract: In the present invention, a thin film capacitor, having a dielectric layer of a metal oxide having perovskite crystal structure, is formed on a first substrate before the capacitor is transferred onto a second substrate on which an electronic circuit has been formed. Thereafter, patterning of the capacitor and electrical connection are to be carried out.

Abstract translation: 在本发明中，在将电容器转印到其上形成有电子电路的第二基板上之后，在第一基板上形成具有具有钙钛矿晶体结构的金属氧化物的电介质层的薄膜电容器。 此后，将进行电容器的图案化和电连接。

公开(公告)号：US06291778B1

公开(公告)日：2001-09-18

申请号：US08765451

申请日：1997-01-22

Applicant: Motoo Asai ,  Masato Kawade ,  Shinji Hiratuka

Inventor： Motoo Asai ,  Masato Kawade ,  Shinji Hiratuka

IPC: H01R909

CPC classification number: H05K3/3457 ,  H05K1/112 ,  H05K3/184 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/0588

Abstract: This invention is to provide a printed circuit board suitable for the high densification of mounting parts using a solder bump and for the improvements of connection reliability and mounting reliability, and proposes a printed circuit board comprising a mounting pad provided with a solder bump by covering a mounting surface with a solder resist, characterized in that a position of forming the solder bump is arranged so as to match with a position of a viahole, or a size of opening portion formed in the solder resist is made larger than a size of a land of the viahole so as not to overlap the solder resist with the viahole.

Abstract translation: 本发明是提供一种印刷电路板，其适用于使用焊料凸块的安装部件的高致密度，并且用于提高连接可靠性和安装可靠性，并且提出了一种印刷电路板，其包括通过覆盖 安装表面具有阻焊剂，其特征在于，形成焊料凸点的位置被布置成与通孔的位置匹配，或者形成在阻焊层中的开口部分的尺寸大于焊盘的尺寸 以防止阻焊剂与通孔重叠。

公开(公告)号：US20010013425A1

公开(公告)日：2001-08-16

申请号：US09815047

申请日：2001-03-23

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

IPC: H05K001/11

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/007 ,  H05K3/045 ,  H05K3/108 ,  H05K3/20 ,  H05K3/205 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49345

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract translation: 一种多层结构的基板，具有多组绝缘层和布线层，并且具有用于安装半导体元件的一个面和将要设置外部连接端子的另一个面，用于安装半导体的面 元件设置有要接合到半导体元件的电极端子的焊盘，另一个面设置有焊接到外部连接端子，例如由焊球形成的端子，并且两个布线层 绝缘层的侧面通过穿过绝缘层的通孔相互连接，其中要结合到半导体元件的电极端子的焊盘的表面是平坦的并且在同一平面中。 还公开了制造这种多层基板的方法。

公开(公告)号：US20010008650A1

公开(公告)日：2001-07-19

申请号：US09461039

申请日：1999-12-15

Inventor： YASUAKI SEKI ,  SHIGENORI SHIRATORI ,  KENJI SUZUKI

IPC: B05D005/12

CPC classification number: H05K3/4673 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2203/0759 ,  H05K2203/085 ,  H05K2203/1105 ,  Y10T428/24917 ,  Y10T428/31681 ,  Y10T428/31728

Abstract: In a manufacturing method of a printed circuit board comprising a process of coating insulative resin on a surface of a printed circuit board having a blind hole and a process of filling up the insulative resin in the blind hole, the printed circuit board coated with the insulative resin is kept in a low pressure atmosphere of 1.3 to 666 hPa, and then the insulative resin is hardened, so that the insulative resin is filled up in the blind hole appropriately.

Abstract translation: 在一种印刷电路板的制造方法中，包括在具有盲孔的印刷电路板的表面上涂覆绝缘树脂的过程和将盲孔中的绝缘树脂填充的过程，印刷电路板涂覆有绝缘体 将树脂保持在1.3〜666hPa的低压气氛中，然后使绝缘树脂硬化，使绝缘树脂适当地填充在盲孔中。

公开(公告)号：US06251766B1

公开(公告)日：2001-06-26

申请号：US09388755

申请日：1999-09-02

Applicant: Kishor V. Desai ,  Amit K. Sarkhel

Inventor： Kishor V. Desai ,  Amit K. Sarkhel

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract translation: 用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。 该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。 台阶或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。

公开(公告)号：US06188028B1

公开(公告)日：2001-02-13

申请号：US09094089

申请日：1998-06-09

Applicant: Belgacem Haba ,  Masud Beroz

Inventor： Belgacem Haba ,  Masud Beroz

IPC: H01R909

CPC classification number: H05K3/4617 ,  H01R12/523 ,  H05K3/325 ,  H05K3/4647 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1184 ,  Y10T29/49126

Abstract: A multilayer structure includes a plurality of stacked circuit panels interconnected by posts extending through each panel. Circuit traces provided on one or both surfaces of each circuit panel interconnect the connectors in a predetermined pattern. The connectors are provided with a blind via which is in electrical contact with a pair of contact pads on either surface of the circuit panel. One of the contact pads has an opening to allow access of a connecting post to the interior of the blind via, the other contact pad having a protruding post. The circuit panels are interconnected by inserting the post of one circuit panel into the blind via of an adjacent circuit panel.

Abstract translation: 多层结构包括通过延伸穿过每个面板的柱相互连接的多个堆叠电路板。 设置在每个电路板的一个或两个表面上的电路迹线以预定图案互连连接器。 连接器设置有盲孔，电路板与电路板的任一表面上的一对接触焊盘电接触。 接触垫中的一个具有开口以允许连接柱进入盲孔的内部，另一个接触垫具有突出的柱。 通过将一个电路板的柱插入相邻电路板的盲孔中，将电路板互连。

公开(公告)号：US6098282A

公开(公告)日：2000-08-08

申请号：US34072

申请日：1998-03-03

Applicant: Jerome Albert Frankeny ,  Richard Francis Frankeny ,  Terry Frederick Hayden ,  Ronald Lann Imken ,  Janet Louise Rice

Inventor： Jerome Albert Frankeny ,  Richard Francis Frankeny ,  Terry Frederick Hayden ,  Ronald Lann Imken ,  Janet Louise Rice

IPC: H05K1/16 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K3/462 ,  H05K1/162 ,  H05K3/4641 ,  H01L2224/81385 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0307 ,  H05K3/4623 ,  Y10T29/435 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability. A multilayer composite laminar stackable circuit board structure is created using, as appropriate, layers having metallic cores and layers having capacitively configured cores. The multilayer laminar stackable circuit board provides direct vertical connection between surface mounted electronic components and the power, signal and capacitive decoupling layers of the composite board through the dendrites and joining metallurgy of the via and plug formations.

Abstract translation: 用于制造精细间距图案多层印刷电路板的方法和装置，其包括提供功率分配，信号分配和电容去耦的层叠堆叠板层。 在一个方面，本发明涉及通过金属芯开始制造板层，图案化芯，选择性地将芯包围在电介质中，选择性地沉积金属以形成通孔，插塞和信号线，以及用连接冶金形成树突 在通孔和插头上，以从板层的平面上方或下方提供可堆叠连接。 在另一方面，本发明涉及使用溶胶 - 凝胶法在金属片上形成薄的高介电常数结晶膜，随后在高介电常数膜上沉积金属层。 该膜用作电容器层的电介质，其后连续地被图案化，被电介质覆盖，并且已经选择性地沉积用于互连电容器和形成通孔的金属层。 然后通孔的端部经历树枝状生长并连接冶金以提供可堆叠的互连能力。 使用适当的方式，使用具有金属芯层和具有电容配置芯的层来形成多层复合层叠堆叠电路板结构。 多层层叠堆叠电路板通过树枝状晶体和连接通孔和插塞结构的冶金，提供表面贴装的电子元件与复合板的功率，信号和电容去耦层之间的直接垂直连接。

公开(公告)号：US6093443A

公开(公告)日：2000-07-25

申请号：US190619

申请日：1998-11-12

Applicant: Jurgen Schulz-Harder ,  Karl Exel

Inventor： Jurgen Schulz-Harder ,  Karl Exel

IPC: H05K1/03 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  B05D5/12

CPC classification number: H05K3/428 ,  H05K3/38 ,  H05K3/421 ,  H05K1/0306 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0384 ,  H05K2203/0542 ,  H05K2203/1105 ,  H05K3/108 ,  H05K3/181 ,  H05K3/427 ,  Y10T29/49128

Abstract: The invention relates to a novel process for producing a copper ceramic substrate with at least one through-plated hole, with a ceramic layer which has at least one opening for the through-plating, on one surface side is provided with a first metal coating and on the opposite surface side with a second metal coating which extends into at least one opening and is connected to the first metal coating, for formation of the first metal coating a copper foil being applied by DCB technique to one surface side of the ceramic layer.

Abstract translation: 本发明涉及一种具有至少一个通孔的铜陶瓷基板的制造方法，在一个表面侧上具有至少一个用于贯通镀层的开口的陶瓷层设置有第一金属涂层和 在相对的表面侧上具有延伸到至少一个开口中并连接到第一金属涂层的第二金属涂层，用于通过DCB技术形成第一金属涂层的铜箔到陶瓷层的一个表面侧。

公开(公告)号：US06021564A

公开(公告)日：2000-02-08

申请号：US159140

申请日：1998-09-23

Applicant: David A. Hanson

Inventor： David A. Hanson

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/11 ,  H01K3/10

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/66 ,  H05K1/115 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09627 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

Abstract translation: 一种通过提供第一导电层在叠层基板中制造低电感导电通孔的方法。 在第一导电层上形成第一电介质层。 在第一电介质层上形成第二导电层。 第一导电路径形成在沿着第一节点和第二节点之间的第一路由延伸的第一导电层中。 第一导电盲通孔在第二节点处连接到第一导电路径，其中第一通孔形成在第二节点处的第一介电层中。 最后，在连接到第一盲通孔的第二导电层中形成第二导电路径。 第二导电路径沿着第二路径在第三节点和第一盲孔之间延伸。 第二路线与第一路线的至少一部分相同。

公开(公告)号：US6002172A

公开(公告)日：1999-12-14

申请号：US815238

申请日：1997-03-12

Applicant: Kishor V. Desai ,  Amit K. Sarkhel

Inventor： Kishor V. Desai ,  Amit K. Sarkhel

IPC: H01L21/60 ,  H01L23/485 ,  H05K1/11 ,  H05K3/34 ,  H01L21/66 ,  H01L29/34

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H05K1/111 ,  H05K3/3436 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/112 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract translation: 用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。 该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。 台阶或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。