公开(公告)号：US08043953B2

公开(公告)日：2011-10-25

申请号：US12521936

申请日：2008-01-15

申请人： Hideya Murai ,  Yuji Kayashima ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Takuo Funaya

发明人： Hideya Murai ,  Yuji Kayashima ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Takuo Funaya

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L24/19 ,  B23K26/389 ,  H01L21/76802 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.

摘要翻译： 可以容易地制造的半导体器件可以包括大量的焊盘，并且可以是薄的，并且提供其制造方法。 半导体器件的特征在于，半导体器件包括LSI芯片，设置在LSI芯片上并由非感光树脂制成的绝缘层，所述绝缘层包括在与外部连接的焊盘相对应的位置中的通孔，以及布线 所述层通过所述通孔延伸到所述外部连接的焊盘，并且所述通孔的至少一部分通过用激光照射所述绝缘层而形成。

公开(公告)号：US07674989B2

公开(公告)日：2010-03-09

申请号：US11449673

申请日：2006-06-09

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H01R12/04

CPC分类号： H05K1/115 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2203/1476 ,  Y10T29/49165

摘要： A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

摘要翻译： 一种用于安装具有多个布线层的半导体元件或电子元件的布线板，设置在这些布线层之间的绝缘层，以及设置在绝缘层上并将布线层电连接的通孔。 在该布线板中，通过多个相似形状（圆圈）的部分重叠，获得与布线层平行的平面中的通孔的截面形状。 通过最小化增加密度的障碍物，有效地增加通孔的横截面积，并且通过使通孔的横截面形状成为由通孔形成的形状来防止布线电阻增加，可以在半导体元件中获得稳定的操作 多个类似形状的部分重叠。

公开(公告)号：US20060283629A1

公开(公告)日：2006-12-21

申请号：US11449673

申请日：2006-06-09

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H05K1/11 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2203/1476 ,  Y10T29/49165

摘要： A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

摘要翻译： 一种用于安装具有多个布线层的半导体元件或电子元件的布线板，设置在这些布线层之间的绝缘层，以及设置在绝缘层上并将布线层电连接的通孔。 在该布线板中，通过多个相似形状（圆圈）的部分重叠，获得与布线层平行的平面中的通孔的横截面形状。 通过最小化增加密度的障碍物，有效地增加通孔的横截面积，并且通过使通孔的横截面形状成为由通孔形成的形状来防止布线电阻增加，可以在半导体元件中获得稳定的操作 多个类似形状的部分重叠。

公开(公告)号：US07838779B2

公开(公告)日：2010-11-23

申请号：US11452933

申请日：2006-06-15

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K3/0055 ,  H05K3/20 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/09863 ,  H05K2203/0796 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.

摘要翻译： 在由板状绝缘膜的一面形成的凹部形成有由布线体和蚀刻阻挡层构成的下层布线的布线基板，在基板绝缘膜的另一面形成有上层布线， 绝缘膜，上层布线和下层布线的布线体通过形成在基板绝缘膜上的通孔相互连接。 通孔为桶形，钟形或波纹管状。

公开(公告)号：US20090294951A1

公开(公告)日：2009-12-03

申请号：US12521936

申请日：2008-01-15

申请人： Hideya Murai ,  Yuji Kayashima ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Takuo Funaya

发明人： Hideya Murai ,  Yuji Kayashima ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Takuo Funaya

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L24/19 ,  B23K26/389 ,  H01L21/76802 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.

摘要翻译： 可以容易地制造的半导体器件可以包括大量的焊盘，并且可以是薄的，并且提供其制造方法。 半导体器件的特征在于，半导体器件包括LSI芯片，设置在LSI芯片上并由非感光树脂制成的绝缘层，所述绝缘层包括在与外部连接的焊盘相对应的位置中的通孔，以及布线 所述层通过所述通孔延伸到所述外部连接的焊盘，并且所述通孔的至少一部分通过用激光照射所述绝缘层而形成。

公开(公告)号：US20060283625A1

公开(公告)日：2006-12-21

申请号：US11452933

申请日：2006-06-15

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

IPC分类号： H05K1/11 ,  H05K1/03

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K3/0055 ,  H05K3/20 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/09863 ,  H05K2203/0796 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.

摘要翻译： 在由板状绝缘膜的一面形成的凹部形成有由布线体和蚀刻阻挡层构成的下层布线的布线基板，在基板绝缘膜的另一面形成有上层布线， 绝缘膜，上层布线和下层布线的布线体通过形成在基板绝缘膜上的通孔相互连接。 通孔为桶形，钟形或波纹管状。

公开(公告)号：US20100244231A1

公开(公告)日：2010-09-30

申请号：US12739302

申请日：2008-10-22

申请人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

发明人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

IPC分类号： H01L23/12 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.

摘要翻译： 半导体器件包括：半导体元件; 支撑基板，布置在所述半导体元件的与其表面相对的表面上，所述支撑基板设置有焊盘，所述支撑基板的面积比所述半导体元件宽; 在所述支撑基板上的掩埋绝缘层，用于将所述半导体元件埋入其中; 一个扇形互连从焊盘引出到掩埋绝缘层上的比半导体元件更外周的区域; 以及加强部，布置在半导体元件的外周的顶部的预设区域中，用于增加掩埋绝缘层的机械强度和扇出互连。

公开(公告)号：US08766440B2

公开(公告)日：2014-07-01

申请号：US13582128

申请日：2011-01-25

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

IPC分类号： H01L23/52

CPC分类号： H05K1/186 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H05K3/4644 ,  H01L2924/00

摘要： A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

摘要翻译： 包括内置半导体元件的布线板包括半导体元件，覆盖半导体元件的外周侧表面的外围绝缘层，设置在布线基板的上表面侧的上表面侧布线，以及下部 设置在布线基板的下表面侧的表面侧配线。 半导体元件包括：第一布线结构层，包括交替设置在半导体基板上的第一布线和第一绝缘层;以及第二布线结构层，包括交替设置在第一布线结构层上的第二布线和第二绝缘层。 上表面侧布线包括经由第二布线电连接到第一布线的布线。 第二布线比第一布线厚，比上表面布线薄。 第二绝缘层由树脂材料形成，并且比第一绝缘层厚。

公开(公告)号：US20130127037A1

公开(公告)日：2013-05-23

申请号：US13638421

申请日：2011-03-03

申请人： Kentaro Mori ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Daisuke Ohshima ,  Yoshiki Nakashima ,  Hideya Murai

发明人： Kentaro Mori ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Daisuke Ohshima ,  Yoshiki Nakashima ,  Hideya Murai

IPC分类号： H01L23/34

CPC分类号： H01L23/34 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/04 ,  H01L24/12 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10342 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1435 ,  H01L2924/145 ,  H05K1/0203 ,  H05K1/185 ,  H05K2201/10515 ,  H01L2924/3512 ,  H01L2924/00

摘要： An object of the present invention is to provide a semiconductor device built-in substrate, which can be made thin and can suppress occurrence of warpage. The present invention provides a semiconductor substrate which is featured by including a first semiconductor device serving as a substrate, a second semiconductor device placed on the circuit surface side of the first semiconductor device in the state where the circuit surfaces of the first and second semiconductor devices are placed to face in the same direction, and an insulating layer incorporating therein the second semiconductor device, and which is featured in that a heat dissipation layer is formed at least between the first semiconductor device and the second semiconductor device, and in that the heat dissipation layer is formed on the first semiconductor device so as to extend up to the outside of the second semiconductor device.

摘要翻译： 本发明的一个目的是提供一种内置半导体器件的基板，它可以制成薄而可以抑制翘曲的发生。 本发明提供一种半导体衬底，其特征在于包括：第一半导体器件，用作衬底;第二半导体器件，其位于第一半导体器件的电路表面侧，处于第一和第二半导体器件的电路表面的状态 被放置成面向相同的方向，并且其中包含第二半导体器件的绝缘层，其特征在于至少在第一半导体器件和第二半导体器件之间形成散热层，并且其中的热量 散热层形成在第一半导体器件上，以便延伸到第二半导体器件的外部。

公开(公告)号：US08344498B2

公开(公告)日：2013-01-01

申请号：US12739302

申请日：2008-10-22

申请人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

发明人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

IPC分类号： H01L23/02

CPC分类号： H01L23/528 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.

摘要翻译： 半导体器件包括：半导体元件; 支撑基板，布置在所述半导体元件的与其表面相对的表面上，所述支撑基板设置有焊盘，所述支撑基板的面积比所述半导体元件宽; 在所述支撑基板上的掩埋绝缘层，用于将所述半导体元件埋入其中; 一个扇形互连从焊盘引出到掩埋绝缘层上的比半导体元件更外周的区域; 以及加强部，布置在半导体元件的外周的顶部的预设区域中，用于增加掩埋绝缘层的机械强度和扇出互连。