中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

79 records (took 0.021 seconds)

    STACKED-GATE SUPER-JUNCTION MOSFET
    22.
    发明申请
    STACKED-GATE SUPER-JUNCTION MOSFET 有权

    公开(公告)号：US20180012994A1

    公开(公告)日：2018-01-11

    申请号：US15224835

    申请日：2016-08-01

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA

    IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265

    CPC classification number: H01L29/7827 ,  H01L21/26513 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/36 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7811 ,  H01L29/7813

    Abstract: A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    25.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20170076949A1

    公开(公告)日：2017-03-16

    申请号：US15358361

    申请日：2016-11-22

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Michael THOMASON ,  Mohammed Tanvir QUDDUS ,  James MORGAN ,  Mihir MUDHOLKAR ,  Scott DONALDSON ,  Gordon M. GRIVNA

    IPC: H01L21/285 ,  H01L29/47 ,  H01L29/872 ,  H01L29/66

    CPC classification number: H01L21/28537 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/76883 ,  H01L21/76889 ,  H01L29/401 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66143 ,  H01L29/8725

    Abstract: A number of variations may include a method that may include depositing a first layer on a first semiconductor layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal. A second layer may comprise a material constructed and arranged to scavenge semiconductor material migrating from the first semiconductor layer during annealing may be deposited over the first layer. The first semiconductor layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with the semiconductor material to form a Schottky barrier structure during the first annealing act.

    Abstract translation: 许多变型可以包括一种方法，其可以包括相对于形成在第一半导体外延层中的至少一个沟槽结构，在覆盖位置的第一半导体层上沉积第一层。 第一层可以包括第一金属和第二金属。 第二层可以包括构造和布置为清除在退火期间从第一半导体层迁移的半导体材料的材料可以沉积在第一层上。 可以对第一半导体层进行至少第一退火处理以提供第一结构。 可以剥离第一结构的至少一部分以去除在半导体材料中未反应的任何第一层，以在第一退火行为期间形成肖特基势垒结构。

    METHOD OF FORMING A TRANSISTOR AND STRUCTURE THEREFOR
    26.
    发明申请
    METHOD OF FORMING A TRANSISTOR AND STRUCTURE THEREFOR 有权
    形成晶体管及其结构的方法

    公开(公告)号：US20160380079A1

    公开(公告)日：2016-12-29

    申请号：US15261308

    申请日：2016-09-09

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Gordon M. GRIVNA

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40

    CPC classification number: H01L29/66666 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

    Abstract: In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

    Abstract translation: 在一个实施例中，半导体器件形成为包括延伸到半导体材料中的栅极结构，该半导体材料位于半导体材料的第一区域下方。 栅极结构包括导体和栅极绝缘体，栅极绝缘体具有位于栅极导体与栅极导体之下的半导体材料的第一部分之间的第一部分。 半导体材料的第一部分被配置为形成在栅极导体下面的晶体管的沟道区。 栅极结构还可以包括覆盖栅极导体并且在屏蔽导体和栅极导体之间​​具有屏蔽绝缘体的屏蔽导体。 屏蔽绝缘体还可以具有位于屏蔽导体和栅极绝缘体的第二部分之间的第二部分和覆盖屏蔽导体的第三部分。

    MONOLITHIC SEMICONDUCTOR DEVICE ASSEMBLIES
    28.
    发明申请
    MONOLITHIC SEMICONDUCTOR DEVICE ASSEMBLIES 有权

    公开(公告)号：US20250126853A1

    公开(公告)日：2025-04-17

    申请号：US18988822

    申请日：2024-12-19

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

    IPC: H10D62/10 ,  H01L21/762 ,  H01L25/07 ,  H10D62/85

    Abstract: In a general aspect, a method includes forming, in a semiconductor device layer disposed on a semiconductor substrate, an opening between a first semiconductor device stack included in the semiconductor device layer and a second semiconductor device stack included in the semiconductor device layer. The method also includes forming a trench in the semiconductor substrate between the first semiconductor device stack and the second semiconductor device stack, the trench corresponding with the opening. The method further includes filling the trench with a first dielectric material, thinning the semiconductor substrate to expose the first dielectric material and separate the semiconductor substrate into a first substrate portion and a second substrate portion, and forming a layer of a second dielectric material on the first substrate portion, the second substrate portion and the exposed first dielectric material.

    STRUCTURES AND METHODS FOR SOURCE-DOWN VERTICAL SEMICONDUCTOR DEVICE
    30.
    发明申请
    STRUCTURES AND METHODS FOR SOURCE-DOWN VERTICAL SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220293781A1

    公开(公告)日：2022-09-15

    申请号：US17805131

    申请日：2022-06-02

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Gordon M. GRIVNA

    IPC: H01L29/78 ,  H01L29/06 ,  H01L21/78 ,  H01L23/48

    Abstract: A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.

Patent Agency Ranking