公开(公告)号：US09728458B2

公开(公告)日：2017-08-08

申请号：US14416895

申请日：2013-07-08

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bernard Aspar ,  Chrystelle Lagahe Blanchard

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/683 ,  H01L33/00

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/7813 ,  H01L33/0079

Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.

公开(公告)号：US09716164B2

公开(公告)日：2017-07-25

申请号：US14430513

申请日：2013-09-03

Applicant: Soitec

Inventor： Mariam Sadaka

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L21/683 ,  H01L29/20 ,  H01L23/36 ,  H01L21/762 ,  H01L29/201 ,  H01L29/66 ,  H01L29/417 ,  H01L23/00

CPC classification number: H01L29/7787 ,  H01L21/02425 ,  H01L21/0254 ,  H01L21/6835 ,  H01L21/76256 ,  H01L23/36 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7788 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29147 ,  H01L2224/29184 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/83895 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.

公开(公告)号：US09349865B2

公开(公告)日：2016-05-24

申请号：US14938545

申请日：2015-11-11

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L29/66 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

公开(公告)号：US20160086974A1

公开(公告)日：2016-03-24

申请号：US14830332

申请日：2015-08-19

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bich-Yen Nguyen ,  Ionut Radu

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7847

Abstract: Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.

Abstract translation: 制造半导体结构的方法包括将离子注入到多层衬底上的应变半导体层的第二区域中，以使应变半导体层的第二区域中的部分晶体半导体材料非晶化，而不会使应变半导体的第一区域失活 层。 非晶区域被重结晶，并且元件在半导体层内扩散以富集在应变半导体层的第二区域的一部分中的扩散元件的浓度，并且相对于第一区域的第一区域的应变状态改变其中的应变状态 应变半导体层。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括半导体层的第一区域的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括半导体层的第二区域的一部分。

公开(公告)号：US09165945B1

公开(公告)日：2015-10-20

申请号：US14489798

申请日：2014-09-18

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bich-Yen Nguyen ,  Ionut Radu

IPC: H01L31/18 ,  H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7847

Abstract: Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.

Abstract translation: 制造半导体结构的方法包括将离子注入到多层衬底上的应变半导体层的第二区域中，以使应变半导体层的第二区域中的部分晶体半导体材料非晶化，而不会使应变半导体的第一区域失活 层。 非晶区域被重结晶，并且元件在半导体层内扩散以富集在应变半导体层的第二区域的一部分中的扩散元件的浓度，并且相对于第一区域的第一区域的应变状态改变其中的应变状态 应变半导体层。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括半导体层的第一区域的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括半导体层的第二区域的一部分。

公开(公告)号：US09041214B2

公开(公告)日：2015-05-26

申请号：US13900157

申请日：2013-05-22

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/52 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括将原子物质注入到载体晶粒或晶片中以在载体晶粒或晶片内形成弱化区域，并将载体晶片或晶片结合到半导体结构。 可以在使用载体晶片或晶片来处理半导体结构的同时对半导体结构进行处理。 半导体结构可以结合到另一个半导体结构，并且载体晶片或晶片可以沿其中的弱化区域分割。 使用这种方法制造粘合的半导体结构。

公开(公告)号：US09553014B2

公开(公告)日：2017-01-24

申请号：US14694794

申请日：2015-04-23

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括将原子物质注入到载体晶粒或晶片中以在载体晶粒或晶片内形成弱化区域，并将载体晶片或晶片结合到半导体结构。 可以在使用载体晶片或晶片来处理半导体结构的同时对半导体结构进行处理。 半导体结构可以结合到另一个半导体结构，并且载体晶片或晶片可以沿其中的弱化区域分割。 使用这种方法制造粘合的半导体结构。

公开(公告)号：US09391011B2

公开(公告)日：2016-07-12

申请号：US14642196

申请日：2015-03-09

Applicant: Soitec

Inventor： Mariam Sadaka

IPC: H01L21/70 ,  H01L23/498 ,  H01L23/473 ,  B01L3/00 ,  H01L21/20 ,  H01L23/367 ,  H01L23/46 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00

CPC classification number: H01L23/49827 ,  B01L3/502707 ,  B01L2300/0864 ,  B01L2300/0867 ,  B01L2300/0874 ,  B01L2300/0887 ,  H01L21/2007 ,  H01L23/367 ,  H01L23/46 ,  H01L23/473 ,  H01L23/49822 ,  H01L24/14 ,  H01L24/16 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/13011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17519 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.

公开(公告)号：US20150255591A1

公开(公告)日：2015-09-10

申请号：US14430513

申请日：2013-09-03

Applicant: SOITEC

Inventor： Mariam Sadaka

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L21/02425 ,  H01L21/0254 ,  H01L21/6835 ,  H01L21/76256 ,  H01L23/36 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7788 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29147 ,  H01L2224/29184 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/83895 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.

Abstract translation: 形成半导体器件的方法包括在第一沉积室中的第一衬底上外延生长III-V基极层。 III-V基层从第一衬底转移到第二衬底，并且在与第一沉积室分离的第二沉积室中在III-V基底层上外延生长至少一个III-V器件层，而III -V基层设置在第二基板上。 第一衬底的平均热膨胀系数（CTE）比由III-V基层显示的平均CTE高于第二衬底所呈现的平均CTE。 可以使用这样的方法制造半导体器件。

公开(公告)号：US20150228535A1

公开(公告)日：2015-08-13

申请号：US14694794

申请日：2015-04-23

Applicant: SOITEC

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括将原子物质注入到载体晶粒或晶片中以在载体晶粒或晶片内形成弱化区域，并将载体晶片或晶片结合到半导体结构。 可以在使用载体晶片或晶片来处理半导体结构的同时对半导体结构进行处理。 半导体结构可以结合到另一个半导体结构，并且载体晶片或晶片可以沿其中的弱化区域分割。 使用这种方法制造粘合的半导体结构。