公开(公告)号：US07132358B2

公开(公告)日：2006-11-07

申请号：US10922172

申请日：2004-08-20

申请人： Se-Young Jeong ,  Jin-Hak Choi ,  Nam-Seog Kim ,  Kang-Wook Lee

发明人： Se-Young Jeong ,  Jin-Hak Choi ,  Nam-Seog Kim ,  Kang-Wook Lee

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  Y10S438/951 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a second UBM layer may be formed on the first photoresist pattern. A second photoresist pattern may be formed that exposes the first UBM layer and covers the second UBM layer. A solder bump may be formed in the opening. The second photoresist pattern and the first photoresist pattern may be removed using a stripper, thereby removing the second UBM layer by a lift-off method.

摘要翻译： 形成焊料凸点的方法可以包括在具有焊盘的晶片上形成第一光致抗蚀剂图案。 第一光致抗蚀剂图案可以具有露出垫的一部分的开口。 可以在焊盘上形成第一凸点下冶金（UBM）层，并且可以在第一光致抗蚀剂图案上形成第二UBM层。 可以形成第二光致抗蚀剂图案，其暴露第一UBM层并覆盖第二UBM层。 可以在开口中形成焊料凸块。 可以使用剥离剂除去第二光致抗蚀剂图案和第一光致抗蚀剂图案，从而通过剥离方法去除第二UBM层。

公开(公告)号：US20050285250A1

公开(公告)日：2005-12-29

申请号：US11089361

申请日：2005-03-25

申请人： Se-Young Jeong ,  Kang-Wook Lee

发明人： Se-Young Jeong ,  Kang-Wook Lee

IPC分类号： H01L23/12 ,  H01L23/02 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/1146 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/81 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： The chip package includes a first and second semiconductor chip. The first semiconductor chip has a first connection structure that electrically connects to a bond pad on a first surface of the first semiconductor chip. The second semiconductor chip has a second connection structure. The second connection structure is electrically connected to a bond pad on a first surface of the second semiconductor chip and extends through the second semiconductor chip to a second surface of the second semiconductor chip. A portion of the second connection structure extending to the second surface of the second semiconductor chip is electrically connected to the first connection structure and formed of a harder material than the first connection structure.

摘要翻译： 芯片封装包括第一和第二半导体芯片。 第一半导体芯片具有电连接到第一半导体芯片的第一表面上的接合焊盘的第一连接结构。 第二半导体芯片具有第二连接结构。 第二连接结构电连接到第二半导体芯片的第一表面上的接合焊盘，并且延伸穿过第二半导体芯片到第二半导体芯片的第二表面。 延伸到第二半导体芯片的第二表面的第二连接结构的一部分电连接到第一连接结构，并且由比第一连接结构更硬的材料形成。

公开(公告)号：USRE45781E1

公开(公告)日：2015-10-27

申请号：US14176526

申请日：2014-02-10

申请人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

发明人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L21/70 ,  H01L23/52 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/22

CPC分类号： H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

摘要翻译： 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

公开(公告)号：US08288278B2

公开(公告)日：2012-10-16

申请号：US12270386

申请日：2008-11-13

申请人： Ki-Tae Park ,  Kang-Wook Lee ,  Hyun-Kyoung Kim

发明人： Ki-Tae Park ,  Kang-Wook Lee ,  Hyun-Kyoung Kim

IPC分类号： H01L21/44

CPC分类号： H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.

摘要翻译： 半导体器件包括衬底和穿过衬底的通孔。 半导体器件具有焊盘区域和贯通电极区域。 焊盘覆盖焊盘区域，延伸到通孔电极区域中，并限定通孔电极区域中的开口。 穿通电极通过穿通区域中的垫中的孔下方的半导体衬底延伸。

公开(公告)号：US20120217290A1

公开(公告)日：2012-08-30

申请号：US13438213

申请日：2012-04-03

申请人： Kang-Wook Lee ,  Nathalie Normand ,  Valerie Oberson

发明人： Kang-Wook Lee ,  Nathalie Normand ,  Valerie Oberson

IPC分类号： B23K1/20 ,  B23K35/363

CPC分类号： B23K35/362 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/3601 ,  B23K35/3612 ,  B23K35/3618

摘要： The present invention is directed to flux compositions and uses thereof. One composition comprises an activator and a solvent being a glycerol ethoxylate with a molecular weight of 200-500. Another composition comprises an activator, a solvent being a glycerol ethoxylate with a molecular weight of 200-500 and an amine. A soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

摘要翻译： 本发明涉及助焊剂组合物及其用途。 一种组合物包含活化剂和溶剂，其分子量为200-500的甘油乙氧基化物。 另一组合物包含活化剂，溶剂为分子量为200-500的甘油乙氧基化物和胺。 还提供了一种用于接合物体的焊接方法，包括以下步骤：将焊剂组合物施加到一个或多个物体的至少一部分，并且连接物体。

公开(公告)号：US20120134864A1

公开(公告)日：2012-05-31

申请号：US13387446

申请日：2009-12-02

申请人： Kang-Wook Lee ,  Bum-Dong Sa

发明人： Kang-Wook Lee ,  Bum-Dong Sa

IPC分类号： F01C1/04

CPC分类号： F01C21/02 ,  F04C18/322 ,  F04C18/3564 ,  F04C23/008 ,  F04C23/02 ,  F04C29/0071 ,  F04C29/0085 ,  F04C29/023 ,  F04C2230/603 ,  F04C2240/10 ,  F04C2240/30 ,  F04C2240/40 ,  F04C2240/52 ,  F04C2240/60 ,  F04C2270/12

摘要： The present invention relates to a compressor in which a rotary member suspended on a stationary member is rotated to compress the refrigerant. The rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member, which achieves the structural stability and allows the components to be easily centered and assembled. A refrigerant suction passage and a refrigerant discharge passage are improved such that the refrigerant can be sucked and discharged without a valve.

摘要翻译： 本发明涉及一种压缩机，其中悬挂在静止构件上的旋转构件旋转以压缩制冷剂。 旋转构件悬挂在第一固定构件上并且可旋转地支撑在与第一固定构件间隔开的第二固定构件上，这实现了结构稳定性并且允许构件容易地居中和组装。 制冷剂吸入通路和制冷剂排出通路得到改善，使得制冷剂能够在没有阀的情况下被抽吸和排出。

公开(公告)号：US20100011806A1

公开(公告)日：2010-01-21

申请号：US12289711

申请日：2008-10-31

申请人： Hyuk Nam ,  Kang-Wook Lee ,  Seung-Hyoung Ha ,  Geun-Hyoung Lee

发明人： Hyuk Nam ,  Kang-Wook Lee ,  Seung-Hyoung Ha ,  Geun-Hyoung Lee

IPC分类号： F25B49/02 ,  F25B1/04 ,  H02K21/46 ,  H02P1/44 ,  F25B1/10 ,  F04C18/00 ,  F04C28/02

CPC分类号： F04C18/3564 ,  F04C23/001 ,  F04C23/008 ,  F04C28/06 ,  F04C29/0085 ,  F04C2240/803 ,  F04C2270/56 ,  H02K1/246 ,  H02K17/165 ,  H02K21/46

摘要： The present invention provides a motor, comprising: a stator including a coil wiring portion to which power is supplied; a rotor, which includes conductive bars, flux barriers, and permanent magnets, and rotates through an interactive electromagnetic force between the conductive bars, flux barriers, and permanent magnets and the coil wiring portion of the stator; an integrated capacitor, which is electrically connected to the coil wiring portion and includes two capacitors connected to each other in parallel, an electrical switch serially connected to one of the two capacitors, and a casing on which the two capacitors and the electrical switch are securely mounted.

摘要翻译： 本发明提供一种电动机，其特征在于，包括：定子，包括供给动力的线圈接线部; 转子，其包括导电棒，磁通屏障和永磁体，并且通过导电棒，磁通屏障和永磁体之间的交互电磁力以及定子的线圈布线部分旋转; 集成电容器，其电连接到线圈布线部分并且包括彼此并联连接的两个电容器，串联连接到两个电容器中的一个的电开关，以及壳体，两个电容器和电开关被牢固地连接在该壳体上 安装。

公开(公告)号：US20090305502A1

公开(公告)日：2009-12-10

申请号：US12476793

申请日：2009-06-02

申请人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

发明人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割的凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20080318363A1

公开(公告)日：2008-12-25

申请号：US12213857

申请日：2008-06-25

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

摘要： A stack circuit member may include a first circuit member and a second circuit member. The first and the second circuit members may be electrically and mechanically connected together using a thermocompression bonding method. A photosensitive polymer layer may be interposed between the first circuit member and the second circuit member. A gap fill process and an electrical connection process may be performed at the same time.

摘要翻译： 堆叠电路构件可以包括第一电路构件和第二电路构件。 第一和第二电路构件可以使用热压接法将电气和机械连接在一起。 感光性聚合物层可以设置在第一电路部件和第二电路部件之间。 间隙填充处理和电连接处理可​​以同时进行。

公开(公告)号：US07459774B2

公开(公告)日：2008-12-02

申请号：US11436851

申请日：2006-05-18

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08112 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

摘要： In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with such voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete gap fill. In addition, mechanical reliability is improved, alleviating the problems associated with cracking and delamination, and leading to an improvement in device yield and device reliability.

摘要翻译： 在堆叠式芯片构造及其制造方法中，使用消除下部和上部切屑之间的空隙以及与这种空隙相关的裂纹和分层问题的相对简单的工艺，完全填充下部和上部切屑之间的间隙。 本发明可应用于芯片级接合和晶片级接合方式。 在堆叠芯片或堆叠晶片之前，将光敏聚合物层施加到第一芯片或晶片。 感光性聚合物层被部分固化，使得光敏聚合物层在结构上稳定，同时保持其粘合性能。 第二芯片或晶片被堆叠，对准并且结合到第一芯片或晶片，然后使光敏聚合物层固化以完全结合第一和​​第二芯片或晶片。 以这种方式，在提供完全的间隙填充的同时，大大提高了芯片/晶片之间的粘附。 此外，机械可靠性得到改善，减轻了与开裂和分层相关的问题，从而提高了设备​​的产量和设备的可靠性。