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    Semiconductor structure and method for manufacturing semiconductor structure
    22.
    发明授权
    Semiconductor structure and method for manufacturing semiconductor structure 有权

    公开(公告)号：US10461117B2

    公开(公告)日：2019-10-29

    申请号：US15848600

    申请日：2017-12-20

    Applicant: XINTEC INC.

    Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

    IPC: H01L27/146 ,  H01L21/683 ,  H01L23/00

    Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

    Chip package and method for forming the same
    25.
    发明授权
    Chip package and method for forming the same 有权

    公开(公告)号：US10153237B2

    公开(公告)日：2018-12-11

    申请号：US15461334

    申请日：2017-03-16

    Applicant: XINTEC INC.

    Inventor： Yen-Shih Ho ,  Chia-Sheng Lin ,  Po-Han Lee ,  Wei-Luen Suen

    IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L23/31

    Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

    Sensing chip package and a manufacturing method thereof
    27.
    发明授权
    Sensing chip package and a manufacturing method thereof 有权

    公开(公告)号：US09887229B2

    公开(公告)日：2018-02-06

    申请号：US15226327

    申请日：2016-08-02

    Applicant: XINTEC INC.

    Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng

    IPC: H01L27/146

    CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

    Chip package and manufacturing method thereof
    29.
    发明授权
    Chip package and manufacturing method thereof 有权
    芯片封装及其制造方法

    公开(公告)号：US09406590B2

    公开(公告)日：2016-08-02

    申请号：US14255883

    申请日：2014-04-17

    Applicant: XINTEC INC.

    Inventor： Chia-Sheng Lin ,  Yen-Shih Ho ,  Tsang-Yu Liu

    IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00

    CPC classification number: H01L23/4952 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2224/494 ,  H01L2224/8536 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

    Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和接合焊盘。 半导体芯片具有设置在下表面上的第一导电焊盘和对应于第一导电焊盘的第一孔。 第一孔和隔离层从上表面延伸到下表面以暴露第一导电垫。 再分布金属层设置在隔离层上并具有对应于第一导电焊盘的再分布金属线，再分布金属线通过开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘以将第一导电焊盘电连接到接合焊盘。 还提供了其方法。

    Semiconductor structure with sensor chip and landing pads
    30.
    发明授权
    Semiconductor structure with sensor chip and landing pads 有权
    具有传感器芯片和着陆垫的半导体结构

    公开(公告)号：US09331256B2

    公开(公告)日：2016-05-03

    申请号：US14464570

    申请日：2014-08-20

    Applicant: XINTEC INC.

    Inventor： Wei-Ming Chien ,  Chia-Sheng Lin ,  Tsang-Yu Liu ,  Yen-Shih Ho

    IPC: H01L21/76 ,  H01L27/146 ,  H01L33/62 ,  H01L21/768

    CPC classification number: H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

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