公开(公告)号：US12014959B2

公开(公告)日：2024-06-18

申请号：US17516560

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823456 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66484 ,  H01L29/7831

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

公开(公告)号：US12009265B2

公开(公告)日：2024-06-11

申请号：US18068110

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

公开(公告)号：US12002682B2

公开(公告)日：2024-06-04

申请号：US17783641

申请日：2020-07-23

Applicant: SHANGHAI IC R&D CENTER CO., LTD

Inventor： Yanli Li ,  Yushu Yang ,  Qiang Wu

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816

Abstract: The present invention disclosures a Tip-to-Tip pattern preparation method, comprising: providing a substrate, and sequentially forming a layer to be etched, a first hard mask layer, a second hard mask layer, a sacrificial layer, a first dielectric layer and a first photoresist layer on the substrate, forming a first patterned photoresist layer which has a first Tip-to-Tip pattern by EUV lithography, and transferring the first Tip-to-Tip pattern to the second hard mask layer by etching; then forming a second patterned photoresist layer which has a second Tip-to-Tip pattern by the EUV lithography, and transferring the second Tip-to-Tip pattern to the second hard mask layer by etching; finally, transferring the first Tip-to-Tip pattern and the second Tip-to-Tip pattern to the layer to be etched. The above method needs only performing the EUV lithography twice to form the small-sized Tip-to-Tip pattern with a period halved, that is, the EUV lithography and etching are used for reducing lithography layers and realizing to form the small-sized Tip-to-Tip pattern with the period halved.

公开(公告)号：US12002681B2

公开(公告)日：2024-06-04

申请号：US17515541

申请日：2021-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/3086 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/3085 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

公开(公告)号：US20240162091A1

公开(公告)日：2024-05-16

申请号：US18501124

申请日：2023-11-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Shogo OKITA ,  Toshiyuki TAKASAKI ,  Ryota FURUKAWA

IPC: H01L21/78 ,  H01L21/308

CPC classification number: H01L21/78 ,  H01L21/3086 ,  H01L21/3065

Abstract: The disclosed element chip manufacturing method includes: a first step of imparting hydrophilicity to a first surface 11 of a substrate 1, the first surface 11 including element regions 11A and dicing regions 11B defining the element regions 11A; a second step of applying a raw material liquid containing a water-soluble resin onto the first surface 11, to form a water-soluble resin layer 20 on the first surface 11; a third step of applying a laser beam to the water-soluble resin layer 20 covering the dicing regions 11B, to form openings 20a that expose the dicing regions 11B, in the water-soluble resin layer 20; a fourth step of etching the dicing regions 11B exposed at the openings 20a, with plasma, to obtain element chips 30; and a fifth step of removing the water-soluble resin layer 20 by bringing the element chips 30 into contact with a water-containing cleaning liquid.

公开(公告)号：US20240153771A1

公开(公告)日：2024-05-09

申请号：US18313355

申请日：2023-05-07

Applicant: SHIN-ETSU CHEMICAL CO., LTD.

Inventor： Naoki KOBAYASHI ,  Daisuke KORI ,  Hironori SATOH ,  Toshiharu YANO

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/0332 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02255 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31056 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144

Abstract: The present invention is a composition for forming a metal oxide film, including: (A) a metal oxide nanoparticle; (B) a flowability accelerator containing a resin having a structural unit represented by the following general formula (1); (C) a dispersion stabilizer having two or more benzene rings or having one benzene ring and a structure represented by the following general formula (C-1), and the dispersion stabilizer being composed of an aromatic group-containing compound having a molecular weight of 500 or less; and (D) an organic solvent, wherein the flowability accelerator (B) has a content of 9 mass % or more in an entirety of the composition, a ratio Mw/Mn of 2.50≤Mw/Mn≤9.00, and the flowability accelerator (B) having no cardo structure. Thus, there can be provided a composition for forming a metal oxide film that has excellent dry etching resistance compared with a conventional organic underlayer film material, that has excellent filling property compared with a conventional metal hard mask, that can reduce cracking with forming a thick film, and that has excellent storage stability;

公开(公告)号：US20240147718A1

公开(公告)日：2024-05-02

申请号：US18406592

申请日：2024-01-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H10B41/50 ,  H01L21/033 ,  H01L21/28 ,  H01L21/308 ,  H01L21/321 ,  H01L29/423 ,  H01L29/51 ,  H10B41/10 ,  H10B41/41

CPC classification number: H10B41/50 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3212 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/518 ,  H10B41/10 ,  H10B41/41 ,  H10B43/35

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.

公开(公告)号：US11955559B2

公开(公告)日：2024-04-09

申请号：US17459256

申请日：2021-08-27

Applicant: SAKAI DISPLAY PRODUCTS CORPORATION

Inventor： Yoshiaki Matsushima ,  Shigeru Ishida ,  Ryohei Takakura ,  Satoru Utsugi ,  Nobutake Nodera ,  Takao Matsumoto ,  Satoshi Michinaka

IPC: H01L29/786 ,  G02F1/1368 ,  H01L21/308 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/78678 ,  G02F1/1368 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/78696 ,  G02F2202/103 ,  G02F2202/104 ,  H01L27/124

Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

公开(公告)号：US11955550B2

公开(公告)日：2024-04-09

申请号：US17308324

申请日：2021-05-05

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Fei Zhou

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices is provided. The semiconductor structure includes a semiconductor substrate having a middle region and an edge region adjacent to the middle region, a plurality of first fins formed on the middle region of the semiconductor substrate, a plurality of second fins formed on the edge region of the semiconductor substrate, a first adjustment layer formed on sidewall surfaces of the plurality of first fins and on the middle region of the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and with a top surface lower top surfaces of the plurality of first fins and the plurality of second fins.

公开(公告)号：US11955532B2

公开(公告)日：2024-04-09

申请号：US17080713

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Jenny Hu ,  Anindya Dasgupta ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.