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公开(公告)号：US20240098873A1
公开(公告)日：2024-03-21
申请号：US18521587
申请日：2023-11-28
Applicant: CelLink Corporation
Inventor： Kevin Michael Coakley , Malcom Parker Brown , Dongao Yang , Michael Lawrence Miller , Paul Henry Lego
CPC classification number: H05K1/0201 , H01M50/519 , H05K1/118 , H05K3/007 , H05K3/0073 , H05K3/06 , H05K3/20 , H05K3/281 , H05K3/4623 , H05K3/064 , H05K2201/0145 , H05K2201/015 , H05K2201/0154 , H05K2201/10037 , Y02E60/10
Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.
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公开(公告)号：US20180166372A1
公开(公告)日：2018-06-14
申请号：US15866686
申请日：2018-01-10
Applicant: Shinko Electric Industries Co., Ltd.
Inventor： Noriyoshi SHIMIZU , Yusuke GOZU , Jun FURUICHI , Akio ROKUGAWA , Takashi Ito
IPC: H01L23/498 , H05K1/11 , H01L23/00 , H05K3/46 , H01L25/10 , H01L25/065 , H01L23/538 , H05K1/09 , H05K3/00 , H05K3/38
CPC classification number: H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49894 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/105 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/26175 , H01L2224/2919 , H01L2224/32225 , H01L2224/32237 , H01L2224/73204 , H01L2224/81191 , H01L2224/81444 , H01L2224/81447 , H01L2224/8149 , H01L2224/81801 , H01L2224/83104 , H01L2224/83855 , H01L2224/92125 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/3511 , H05K1/095 , H05K1/111 , H05K1/112 , H05K1/114 , H05K1/115 , H05K3/0073 , H05K3/383 , H05K3/4644 , H05K2201/0195 , H05K2201/09845 , H05K2203/0392 , H01L2924/00014 , H01L2924/014 , H01L2924/01079 , H01L2924/01029 , H01L2924/01047 , H01L2924/0665
Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
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公开(公告)号：US09832888B1
公开(公告)日：2017-11-28
申请号：US15191554
申请日：2016-06-24
Applicant: Avary Holding (Shenzhen) Co., Limited. , HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. , GARUDA TECHNOLOGY CO., LTD.
Inventor： Yan-Lu Li , Mei Yang , Cheng-Jia Li
CPC classification number: H05K3/4644 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0011 , H05K3/0073 , H05K3/02 , H05K3/4038 , H05K2201/095
Abstract: A method of manufacture of a circuit board without annular through-hole rings and thus allowing a higher component density includes a base layer, a first wire pattern layer, and a second wire pattern layer on both sides of the base layer. A portion of the base layer not covered by the first wire pattern layer defines at least one first hole. The circuit board further includes a wire layer. The wire layer includes at least a first portion and a second portion connecting to the first portion. The first portion is filled in the first hole. The second portion is formed on the first portion extending away from the base layer. A diameter of the second portion is less than an aperture diameter of the first hole. The wire layer is electrically conductive between the first wire pattern layer and the second wire pattern layer through the first portion.
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公开(公告)号：US09713261B2
公开(公告)日：2017-07-18
申请号：US14356209
申请日：2012-08-31
Applicant: Jianyuan Song , Weihong Peng , Pingping Xie , Dong Liu
Inventor： Jianyuan Song , Weihong Peng , Pingping Xie , Dong Liu
CPC classification number: H05K3/00 , H05K1/0269 , H05K3/0017 , H05K3/0044 , H05K3/0047 , H05K3/0073 , H05K3/12 , H05K3/188 , H05K3/3452 , H05K3/42 , H05K3/425 , H05K3/428 , H05K3/4623 , H05K3/4629 , H05K2201/09036 , H05K2201/09845 , H05K2203/0315 , H05K2203/162 , Y10T29/49004 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T29/49179
Abstract: A fabrication process of a stepped circuit board comprises A) cutting a circuit board substrate, printing patterns on an inner layer of the circuit board substrate, stepped groove milling of the inner layer, washer milling a washer between the inner layer and an outer layer, brownification and lamination processing on the inner layer, and then drilling holes on an outer layer of the circuit board substrate; B) electroplating the entire circuit board substrate by depositing copper on the outer layer of the circuit board substrate with drilled holes; C) performing pattern transfer by means of through-hole plating of the drilled holes on the circuit board substrate processed by the copper depositing and the electroplating; D) after pattern transferring, grinding a shape of a connecting piece (SET) on the circuit board substrate after the electroplating; E) plugging the drilled holes to form plug holes and printing a solder mask and texts in a silk-screen manner after forming the plug holes; F) depositing nickel immersion gold on the entire circuit board substrate, then printing characters in a silk-screen manner, thereby forming the stepped circuit board; and G) testing and inspecting an electric performance and appearance of the stepped circuit board to fabricate a finished product of the stepped circuit board.
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公开(公告)号：US20170171975A1
公开(公告)日：2017-06-15
申请号：US15426062
申请日：2017-02-07
Applicant: Unimicron Technology Corp.
Inventor： Shu-Sheng Chiang , Ming-Hao Wu , Wei-Ming Cheng
CPC classification number: H05K1/111 , H05K1/0266 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/0073 , H05K3/4038 , H05K3/4092 , H05K3/4644 , H05K3/4697 , H05K2201/09036 , H05K2201/094 , H05K2201/09563 , H05K2201/09781 , H05K2203/0376 , H05K2203/163
Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer. A hole diameter of the opening is smaller than a hole diameter of cavity. A height difference is between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first patterned circuit layer exposed by the opening.
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Patent Agency Ranking
公开(公告)号：US20170171973A1
公开(公告)日：2017-06-15
申请号：US15287718
申请日：2016-10-06
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Shu-Sheng Chiang , Wei-Ming Cheng
CPC classification number: H05K1/111 , H05K1/0266 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/0073 , H05K3/4038 , H05K3/4092 , H05K3/4644 , H05K3/4697 , H05K2201/09036 , H05K2201/094 , H05K2201/09563 , H05K2201/09781 , H05K2203/0376 , H05K2203/163
Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.
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公开(公告)号：US09627194B2
公开(公告)日：2017-04-18
申请号：US14542318
申请日：2014-11-14
Applicant: HZO, Inc.
Inventor： Blake Stevens , Max Sorenson , Sidney Edward Martin, III
CPC classification number: H01L21/02299 , B05C21/005 , H01L21/027 , H01L23/564 , H01L2924/0002 , H05K1/02 , H05K3/0073 , H05K3/28 , H05K3/284 , Y10T29/49002 , H01L2924/00
Abstract: One or more masks may be used to control the application of protective (e.g., moisture-resistant, etc.) coatings to one or more portions of various components of an electronic device during assembly of the electronic device. A method for applying a protective coating to an electronic device includes assembling two or more components of the electronic device with one another. A mask may then be applied to the resulting electronic assembly. The mask may shield selected portions of the electronic assembly, while other portions of the electronic assembly, i.e., those to which a protective coating is to be applied, may remain exposed through the mask. With the mask in place, application of a protective coating to portions of the electronic assembly exposed through the mask may commence. After application of the protective coating, the mask may be removed from the electronic assembly. Embodiments of masked electronic assemblies are also disclosed.
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公开(公告)号：US09549466B2
公开(公告)日：2017-01-17
申请号：US14977658
申请日：2015-12-22
Applicant: Wistron Corporation
Inventor： Jui-Yun Fan , Hui-Lin Lu , Howard Huang , Zheng-Wei Wu
CPC classification number: H05K1/0298 , H05K1/115 , H05K3/0073 , H05K3/341 , H05K3/3447 , H05K3/3452 , H05K3/3484 , H05K3/4664 , H05K2201/09909 , H05K2203/04 , H05K2203/0588 , Y10T29/49165
Abstract: A circuit board includes a circuit board plate, a conductive ring, a solder mask and at least one insulating pad. The circuit board plate includes a surface and a conductive through hole passing through the surface and the circuit board plate, wherein the conductive through hole have a conductive layer disposed on a wall thereof. The conductive ring on the surface surrounds an opening of the conductive through hole on the surface and electrically connects to the conductive layer. The solder mask is disposed on the surface. The conductive ring is exposed outside of the solder mask. The insulating pad has a thickness. The first surface of the insulating pad is adapted to contact the solder mask or the surface and sited at periphery of the conductive ring. The second surface of the insulating pad is adapted for spacing a distance between a solder coating tool and the solder mask.
Abstract translation: 电路板包括电路板板，导电环，焊接掩模和至少一个绝缘垫。 电路板板包括表面和穿过表面的导电通孔和电路板板，其中导电通孔具有布置在其壁上的导电层。 表面上的导电环围绕表面上的导电通孔的开口并与导电层电连接。 焊接掩模设置在表面上。 导电环暴露在焊料掩模的外部。 绝缘垫具有厚度。 绝缘垫的第一表面适于接触焊料掩模或表面并位于导电环的周边。 绝缘垫的第二表面适于间隔焊料涂覆工具和焊接掩模之间的距离。
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公开(公告)号：US09271404B2
公开(公告)日：2016-02-23
申请号：US14029809
申请日：2013-09-18
Applicant: Wistron Corporation
Inventor： Jui-Yun Fan , Hui-Lin Lu , Howard Huang , Zheng-Wei Wu
CPC classification number: H05K1/0298 , H05K1/115 , H05K3/0073 , H05K3/341 , H05K3/3447 , H05K3/3452 , H05K3/3484 , H05K3/4664 , H05K2201/09909 , H05K2203/04 , H05K2203/0588 , Y10T29/49165
Abstract: A circuit board includes a circuit board plate, a conductive ring, a solder mask and at least one insulating pad. The circuit board plate includes a surface and a conductive through hole passing through the surface and the circuit board plate, wherein the conductive through hole have a conductive layer disposed on a wall thereof. The conductive ring on the surface surrounds an opening of the conductive through hole on the surface and electrically connects to the conductive layer. The solder mask is disposed on the surface. The conductive ring is exposed outside of the solder mask. The insulating pad has a thickness. The first surface of the insulating pad is adapted to contact the solder mask or the surface and sited at periphery of the conductive ring. The second surface of the insulating pad is adapted for spacing a distance between a solder coating tool and the solder mask.
Abstract translation: 电路板包括电路板板，导电环，焊接掩模和至少一个绝缘垫。 电路板板包括表面和穿过表面的导电通孔和电路板板，其中导电通孔具有布置在其壁上的导电层。 表面上的导电环围绕表面上的导电通孔的开口并与导电层电连接。 焊接掩模设置在表面上。 导电环暴露在焊料掩模的外部。 绝缘垫具有厚度。 绝缘垫的第一表面适于接触焊料掩模或表面并位于导电环的周边。 绝缘垫的第二表面适于间隔焊料涂覆工具和焊接掩模之间的距离。
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公开(公告)号：US20150296630A1
公开(公告)日：2015-10-15
申请号：US14748859
申请日：2015-06-24
Applicant: Summit Imaging, Inc.
Inventor： Stephenjon Besagar Barredo
IPC: H05K3/34 , H05K1/03 , H05K1/18 , H01L23/00 , H01L23/498
CPC classification number: H05K3/3436 , H01L23/49816 , H01L23/49838 , H01L23/49866 , H01L24/17 , H01L2224/05124 , H01L2924/15311 , H05K1/0313 , H05K1/0393 , H05K1/181 , H05K3/0073 , H05K3/3478 , H05K2201/0154 , H05K2203/041 , H05K2203/043 , H05K2203/0557 , Y02P70/613
Abstract: A device for providing a reliable and robust electrical connection of a chip to a board using a plurality of solder balls, the device including a non-rigid body formed of a thermal resistant material having a top side and a bottom side, the bottom side having an adhesive layer; and an array of openings formed in the body, the array of openings arranged in a pattern that matches a pattern of conductive pads on the board, each opening having a circular plan form shape that is sized to enable a single solder ball to be slideably received in the opening, each opening spaced from adjacent openings by a distance that prevents adjacent solder balls from electrically connecting to each other when the solder balls are subjected to a temperature sufficient to reflow the solder ball.
Abstract translation: 一种用于使用多个焊球提供芯片到板的可靠且牢固的电连接的装置，该装置包括由具有顶侧和底侧的耐热材料形成的非刚性体，底侧具有 粘合层; 以及形成在所述主体中的开口阵列，所述开口阵列布置成与所述板上的导电焊盘的图案匹配的图案，每个开口具有圆形平面形状形状，其尺寸被设计成使得能够可滑动地接收单个焊球 在开口中，每个开口与邻近的开口隔开一段距离，当焊球受到足以回流焊球的温度时，防止相邻的焊球彼此电连接。
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