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    Memory Systems and Methods for Improved Power Management
    331.
    发明公开
    Memory Systems and Methods for Improved Power Management 审中-公开

    公开(公告)号：US20230360695A1

    公开(公告)日：2023-11-09

    申请号：US18203591

    申请日：2023-05-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  G11C7/22

    CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C7/22

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    Memory system with threaded transaction support
    332.
    发明授权
    Memory system with threaded transaction support 有权

    公开(公告)号：US11809712B2

    公开(公告)日：2023-11-07

    申请号：US17586575

    申请日：2022-01-27

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

    CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    HYBRID MEMORY MODULE
    338.
    发明公开
    HYBRID MEMORY MODULE 审中-公开

    公开(公告)号：US20230229593A1

    公开(公告)日：2023-07-20

    申请号：US18152642

    申请日：2023-01-10

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/7203

    Abstract: A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

    Memory system with error detection
    340.
    发明授权
    Memory system with error detection 有权

    公开(公告)号：US11646094B2

    公开(公告)日：2023-05-09

    申请号：US17840765

    申请日：2022-06-15

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G06F11/10

    CPC classification number: G11C29/42 ,  G06F11/1012 ,  G06F11/1016 ,  G06F11/1032 ,  G06F11/1048 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401

    Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

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